Inventor

KING TSU-JAE

US72 patents

⚠️ This page may combine multiple inventors who share the name “KING TSU-JAE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KING TSU-JAE

PROGRESSANT TECHNOLOGIES INC

Charge trapping device and method for implementing a transistor having a negative differential resistance mode

CMOS compatible process for making a tunable negative differential resistance (NDR) device

CMOS-process compatible, tunable NDR (negative differential resistance) device and method of operating same

Insulated-gate field-effect transistor integrated with negative differential resistance (NDR) FET

Method of orperating a dual mode FET &amp; logic circuit having negative differential resistance mode

Dual mode FET &amp; logic circuit having negative differential resistance mode

Silicon on insulator (SOI) negative differential resistance (NDR) based memory device with reduced body effects

Methods of testing/stressing a charge trapping device

Charge trapping device

Enhanced read and write methods for negative differential resistance (NDR) based memory device

N-channel pull-up element and logic circuit

Method of making memory cell utilizing negative differential resistance devices

Method of forming a negative differential resistance device

Negative differential resistance (NDR) memory cell with reduced soft error rate

Charge trapping device and method of forming the same

Enhanced read and write methods for negative differential resistance (NDR) based memory device

Adaptive negative differential resistance device

Negative differential resistance (NDR) elements and memory device using the same

Memory cell using negative differential resistance field effect transistors

Method for configuring a device to include a negative differential resistance (NDR) characteristic

Negative differential resistance (NDR) device and method of operating same

Method for fabricating a dual mode FET and logic circuit having negative differential resistance mode

Method for making both a negative differential resistance (NDR) device and a non-NDR device using a common MOS process

Negative differential resistance (NDR) element and memory with reduced soft error rate

UNIV CALIFORNIA

Dual work function CMOS gate technology based on metal interdiffusion

Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture

Polycrystalline silicon germanium films for forming micro-electromechanical systems

Polycrystalline silicon-germanium films for micro-electromechanical systems application

Damascene process for use in fabricating semiconductor structures having micro/nano gaps

Dual work function CMOS gate technology based on metal interdiffusion

Two bit/four bit SONOS flash memory cell

Ion beam extractor with counterbore

Multiple-thickness gate oxide formed by oxygen implantation

Nano-electro-mechanical memory cells and devices

Complementary field-effect transistors having enhanced performance with a single capping layer

SYNOPSYS INC

Methods of designing an integrated circuit on corrugated substrate

Integrated circuit on corrugated substrate

Method of IC production using corrugated substrate

Segmented channel MOS transistor

Integrated circuit on corrugated substrate

Method of making adaptive negative differential resistance device

Negative differential resistance (NDR) based memory device with reduced body effects

Negative differential resistance field effect transistor for implementing a pull up element in a memory cell

Negative differential resistance load element

XEROX CORP

Reducing leakage current in a thin-film transistor with charge carrier densities that vary in two dimensions

Solid phase epitaxial crystallization of amorphous silicon films on insulating substrates

Solid phase epitaxial crystallization of amorphous silicon films on insulating substrates

TRUSTEES OF LELAND STANFORD UN

Low temperature germanium-silicon on insulator thin-film transistor

KING TSU-JAE

Integrated circuit on corrugated substrate

PROGRESSENT TECHNOLOGIES INC

Charge trapping device and method for implementing a transistor having a configurable threshold

Method of orperating a dual mode FET & logic circuit having negative differential resistance mode

Dual mode FET & logic circuit having negative differential resistance mode