Debug output loosely coupled with processor block

Abstract

An intergrated circuit constructed for easy debug and emulation includes a function clock circuit and an operation circuit operating in synchronism with a function clock. A trace trigger circuit triggers trace operation upon detection of a predetermined condition within the operation circuit. A FIFO buffer receives the trace data which is exported via a trace port. The integrated circuit includes an oscillator clock circuit which may be synchronized with the function clock or a reference clock. The trace trigger circuit and the FIFO input operate on the function clock. The FIFO output and the trace port operate on the oscillator clock. Thus the trace may operate all on the function clock or be split between the function clock and the reference clock. Accordingly, the trace export can operate at a frequency independent of the operation circuit.

What is claimed is:  
     
       1. An integrated circuit comprising: 
       a function clock circuit generating a function clock signal;  
       an operation circuit connected to said function clock circuit operating in synchronism with said function clock;  
       a trace trigger circuit connected to said function clock circuit and said operation circuit, said trace trigger circuit triggering trace of operation of said operation circuit upon detection of a predetermined condition within said operation circuit;  
       a clock circuit including  
       a reference clock input for receiving a reference clock signal,  
       an controllable oscillator circuit generating an oscillator clock signal,  
       a multiplexer having a first input connected to said function clock circuit for receiving said function clock signal, a second input connected to said reference clock input for receiving said reference clock signal, and an output, said multiplexer selecting at said output one of said function clock signal and said reference clock signal,  
       a comparison circuit connected to said multiplexer controlling a frequency of said controllable oscillator circuit to achieve a frequency match between said clock signal selected by said multiplexer and said oscillator clock signal;  
       a trace first-in-first-out buffer having an input connected to said function clock circuit and said operation circuit for storing trace data in synchronism with said function clock signal and an output connected to said controllable clock circuit for outputting trace data in synchronism with said oscillator clock signal; and  
       a trace output port connected to said controllable clock circuit and said output of said trace first-in-first-out buffer outputting trace data in synchronism with said oscillator clock signal.  
     
     
       2. The integrated circuit of  claim 1 , further comprising: 
       an externally writeable clock control register having a mode field indicating one of a function clock mode and a reference clock mode;  
       said multiplexer selecting said function clock signal in said function clock mode and selecting said reference clock signal in said reference clock mode.  
     
     
       3. The integrated circuit of  claim 1 , wherein: 
       said clock control register includes a first divisor field storing a first clock scaling factor and a second divisor field storing a second clock scaling factor;  
       said integrated circuit further comprises a first pre-scalar circuit having a input connected to said output of said first multiplexer and an output connected to said comparator dividing said clock signal selected by said first multiplexer corresponding to said first clock scaling factor; and  
       said integrated circuit further comprises a second pre-scalar circuit having a input connected to said output of said second multiplexer and an output connected to said comparator dividing said clock signal selected by said second multiplexer corresponding to said second clock scaling factor.  
     
     
       4. The integrated circuit of  claim 1 , wherein: 
       said at least one externally writeable clock control register is directly writeable via a bus accessible external to said integrated circuit.  
     
     
       5. The integrated circuit of  claim 1 , wherein: 
       said at least one externally writeable clock control register is indirectly writeable via writing to an indirect access resister which is writeable via a bus accessible external to said integrated circuit.  
     
     
       6. The integrated circuit of  claim 1 , wherein: 
       said at least one externally writeable clock control register is writeable via a serial scan chain accessible external to said integrated circuit.