Apparatus and methods for translating test vectors

Abstract

Apparatus and methods for translating test vectors between a format suitable for use with a standalone integrated circuit tester and a format suitable for use with an in-circuit tester are disclosed. Methods according to the invention include: providing a first test file in a first format that is suitable for use with the standalone integrated circuit tester, and translating the first test file into a second test file in a second format that is suitable for use with the in-circuit tester. Methods according to the invention also include: providing a first test file in a first format that is suitable for use with the in-circuit tester, and translating the first test file into a second test file in a second format that is suitable for use with the standalone integrated circuit tester. Apparatus according to the invention include computer-readable media having stored thereon computer-executable instructions for performing these methods.

We claim:  
     
       1. A method for translating test vectors from a format suitable for use with an integrated circuit tester into a format suitable for use with an in-circuit tester, comprising: 
       providing a first test file in a first format that is suitable for use with the integrated circuit tester for standalone testing of an integrated circuit;  
       translating the first test file into a second test file in a second format that is suitable for use with the in-circuit tester for in-circuit testing of the integrated circuit, comprising the steps of:  
       identifying in the first file, test vector data in the first format;  
       identifying in the first file, pin information in the first format,  
       writing to the second file, test vector data in the second format, the test vector data in the second format corresponding to the test vector data in the first format;  
       writing to the second file, a plurality of pin data in the second format, the plurality of pin data based on the pin information.  
     
     
       2. The method of  claim 1 , wherein the first test file includes a set of test vectors for standalone testing of the integrated circuit. 
     
     
       3. The method of  claim 1 , wherein the first test file includes a set of pin definitions that define pins of the integrated circuit. 
     
     
       4. The method of  claim 1 , wherein the first test file is provided, at least in part, by 
       providing a complete test file that includes test vectors for testing logic within the integrated circuit;  
       selecting a subset of the test vectors included in the complete test file; and  
       including the selected subset in the first test file.  
     
     
       5. The method of  claim 1 , wherein the plurality of pin data includes pin assignment statements, pin definitions, and pin functionality statements. 
     
     
       6. The method of  claim 1 , wherein the first format is IMS format. 
     
     
       7. The method of  claim 1 , wherein the second format is pattern conversion format. 
     
     
       8. A method for translating test vectors from a format suitable for use with an in-circuit tester into a format suitable for use with an integrated circuit tester, comprising: 
       providing a first test file in a first format that is suitable for use with the in-circuit tester for in-circuit testing of an integrated circuit;  
       translating the first test file into a second test file in a second format that is suitable for use with the integrated circuit tester for standalone testing of the integrated circuit, comprising the steps of:  
       identifying in the first file, test vector data in the first format;  
       identifying in the first file, pin information in the first format;  
       writing to the second file, test vector data in the second format, the test vector data in the second format corresponding to the test vector data in the first format;  
       writing to the second file, a plurality of pin data in the second format, the plurality of pin data based on the pin information.  
     
     
       9. The method of  claim 8 , wherein the first test file includes a set of test vectors for in-circuit testing of the integrated circuit. 
     
     
       10. The method of  claim 8 , wherein the first test file includes a set of pin definitions that define pins of the integrated circuit. 
     
     
       11. The method of  claim 8 , wherein the first test file is provided, at least in part, by 
       providing a complete test file that includes test vectors for testing the integrated circuit in a completed printed circuit board assembly;  
       selecting a subset of the test vectors included in the complete test file; and  
       including the selected subset in the first test file.  
     
     
       12. The method of  claim 8 , wherein the plurality of pin data includes pin assignment statements, pin definitions, and pin functionally statements. 
     
     
       13. The method of  claim 8 , wherein the first format is pattern conversion format. 
     
     
       14. The method of  claim 8 , wherein the second format is IMS format. 
     
     
       15. A computer-readable medium having stored thereon computer-executable instructions for performing a method comprising: 
       providing a first test file in a first format that is suitable for use with the integrated circuit tester for standalone testing of an integrated circuit;  
       translating the first test file into a second test file in a second format that is suitable for use with the in-circuit tester for in-circuit testing of the integrated circuit, comprising the steps of:  
       identifying in the first file, test vector data in the first format;  
       identifying in the first file, pin information in the first format;  
       writing to the second file, test vector data in the second format, the test vector data in the second format corresponding to the test vector data in the first format;  
       writing to the second file, a plurality of pin data in the second format, the plurality of pin data based on the pin information.  
     
     
       16. A computer-readable medium having stored thereon computer-executable instructions for performing a method comprising: 
       providing a first test file in a first format that is suitable for use with the in-circuit tester for in-circuit testing of an integrated circuit;  
       translating the first test file into a second test file in a second format that is suitable for use with the integrated circuit tester for standalone testing of the integrated circuit, comprising the steps of:  
       identifying in the first file, test vector data in the first format;  
       identifying in the first file, pin information in the first format;  
       writing to the second file, test vector data in the second format, the test vector data in the second format corresponding to the test vector data in the first format;  
       writing to the second file, a plurality of pin data in the second format, the plurality of pin data based on the pin information.