Semiconductor structure having alignment marks with shallow trench isolation

Abstract

A semiconductor structure including a semiconductor substrate, an isolation trench in the semiconductor substrate, and an alignment trench in the semiconductor substrate is disclosed. The structure also includes a dielectric layer and a metallic layer. The dielectric layer is on the semiconductor substrate and in both the isolation trench and the alignment trench. The dielectric layer fills the isolation trench and does not fill the alignment trench. The metallic layer is on the dielectric layer.

What is claimed is:  
     
       1. A semiconductor structure, comprising: 
       a semiconductor substrate;  
       an isolation trench in the semiconductor substrate;  
       an alignment trench in the semiconductor substrate;  
       a dielectric layer on the semiconductor substrate and in both the isolation trench and the alignment trench, wherein the dielectric layer fills the isolation trench and does not fill the alignment trench;  
       a metallic layer on the dielectric layer, and  
       an etch-stop layer on the metallic layer,  
       wherein the etch-stop layer comprises nitride and the dielectric layer comprises oxide.  
     
     
       2. The semiconductor structure of  claim 1 , wherein the depth of the isolation trench is less than the depth of the alignment trench. 
     
     
       3. The semiconductor structure of  claim 2 , wherein the alignment trench has a depth of at least 3500 angstroms. 
     
     
       4. The semiconductor structure of  claim 2 , wherein the isolation trench has a depth of at least 2000 angstroms. 
     
     
       5. The semiconductor structure of  claim 2 , further comprising a gate layer on the substrate and under the metallic layer.