Reduction of chip carrier flexing during thermal cycling

Abstract

A method and structure for reducing chip carrier flexing during thermal cycling. A semiconductor chip is coupled to a stiff chip carrier (i.e., a chip carrier having an elastic modulus of at least about 3×10 5 psi), and there is no stiffener ring on a periphery of the chip carrier. Without the stiffener ring, the chip carrier is able to undergo natural flexing (in contrast with constrained flexing) in response to a temperature change that induces thermal strains due to a mismatch in coefficient of thermal expansion between the chip and the chip carrier. If the temperature at the chip carrier changes from room temperature to a temperature of about −40° C., a maximum thermally induced displacement of a surface of the chip carrier is at least about 25% less if the stiffener ring is absent than if the stiffener ring is present. Since a propensity for cracking of the stiff chip carrier increases as the thermally induced displacement increases, the present invention, which avoids use of the stiffener ring, improves a structural integrity of the chip carrier.

We claim:  
     
       1. A method of forming an electronic structure, comprising: 
       providing a chip carrier having an elastic modulus of at least about 3×10 5  psi, wherein there is no stiffener ring coupled to a peripheral portion of the chip carrier; and  
       coupling a semiconductor chip to a central portion of the chip carrier, wherein the semiconductor chip has a coefficient of thermal expansion (CTE) of C 1 , wherein the chip carrier has a CTE of C 2 , wherein C 2 >C 1 , and wherein the chip carrier is able to undergo natural flexing in response to thermal stresses caused by a difference between C 2  and C 1 .  
     
     
       2. The method of  claim 1 , wherein the peripheral portion of the chip carrier is essentially exposed, and wherein the peripheral portion of the chip carrier includes about 70% to 90% of the surfaces area of a surface of the chip carrier. 
     
     
       3. The method of  claim 1 , wherein the chip carrier includes an epoxy based material. 
     
     
       4. The method of  claim 1 , wherein the chip carrier includes a material selected from the group consisting of bismalimide-triazine (BT)-Epoxy/Glass, a cyanate ester resin, cyanate ester-epoxy-ePTFE, and combinations thereof. 
     
     
       5. The method of  claim 4 , further comprising forming conductive wiring on a surface of the chip carrier, wherein the surface is selected from the group consisting of a top surface, a bottom surface, and a combination thereof, and wherein the conductive wiring is better able to maintain its structural integrity under a thermally induced displacement of the chip carrier than if the stiffener ring were present. 
     
     
       6. The method of  claim 1 , further comprising forming conductive wiring on a surface of the chip carrier, wherein the surface is selected from the group consisting of a top surface, a bottom surface, and a combination thereof, and wherein the conductive wiring is better able to maintain its structural integrity under a thermally induced displacement of the chip carrier than if the stiffener ring were present. 
     
     
       7. The method of  claim 1 , further comprising subjecting the chip carrier to the thermal stresses caused by the difference between C 2  and C 1 , resting in natural flexing of the chip carrier. 
     
     
       8. The method of  claim 7 , wherein subjecting the chip carrier to the thermal stresses caused by the difference between C 2  and C 1  includes subjecting the chip carrier to a temperature in a range of about 21° C. to about −40° C., resulting in a surface of the chip carrier being maximally displaced by at least about 25% less than if the stiffener ring were coupled to the peripheral portion of the chip carrier. 
     
     
       9. The method of  claim 7 , wherein the chip carrier includes a material selected from the group consisting of bismalimide-triazine (BT)-Epoxy/Glass, a cyanate ester resin, cyanate ester-epoxy-ePTFE, and combinations thereof. 
     
     
       10. The method of  claim 7 , wherein the chip carrier has an isotropic coefficient of thermal expansion (CTE) at a temperature above the glass transition temperature (GTT) of the chip carrier. 
     
     
       11. A method of forming an electronic structure, comprising: 
       providing a chip carrier having an elastic modulus of at least about 3×10 5  psi, wherein there is no stiffener ring coupled to a peripheral portion of the chip carrier; and  
       coupling a semiconductor chip to a central portion of the chip carrier, wherein the chip carrier has an isotropic coefficient of thermal expansion (CTE) at a temperature above the glass transition temperature (GTT) of the chip carrier.  
     
     
       12. The method of  claim 11 , further comprising subjecting the chip carrier to a temperature that is above the GTT. 
     
     
       13. The method of  claim 11 , further comprising forming conductive wiring on a surface of the chip carrier, wherein the surface is selected from the group consisting of a top surface, a bottom surface, and a combination thereof, and wherein the conductive wiring is better able to maintain its structural integrity under a thermally induced displacement of the chip carrier than if the stiffener ring were present. 
     
     
       14. The method of  claim 11 , further comprising subjecting the chip carrier to a temperature that is above the GTT. 
     
     
       15. A method of forming an electronic structure, comprising: 
       providing a chip carrier having an elastic modulus of at least about 3×10 5  psi, wherein there is no stiffener ring coupled to a peripheral portion of the chip carrier, wherein the peripheral portion of the chip carrier includes about 70% to 90% of the surfaces area of a surface of the chip carrier; and  
       coupling a semiconductor chip to a central portion of the chip carrier.  
     
     
       16. The method of  claim 15 , wherein the chip carrier includes an epoxy based material. 
     
     
       17. The method of  claim 15 , wherein the chip carrier has an isotropic coefficient of thermal expansion (CTE) at a temperature above the glass transition temperature (GTT) of the chip carrier. 
     
     
       18. The method of  claim 17 , further comprising forming conductive wiring on a surface of the chip carrier, wherein the surface is selected from the group consisting of a top surface, a bottom surface, and a combination thereof, and wherein the conductive wiring is better able to maintain its structural integrity under a thermally induced displacement of the chip carrier than if the stiffener ring were present. 
     
     
       19. The method of  claim 15 , wherein the chip carrier includes a material selected from the group consisting of bismalimide-triazine (BT)-Epoxy/Glass, a cyanate ester resin, cyanate ester-epoxy-ePTFE, and combinations thereof. 
     
     
       20. The method of  claim 19 , further comprising forming conductive wiring on a surface of the chip carrier, wherein the surface is selected from the group consisting of a top surface, a bottom surface, and a combination thereof, and wherein the conductive wiring is better able to maintain its structural integrity under a thermally induced displacement of the chip carrier than if the stiffener ring were present.