Variable capacitance device and process for manufacturing the same

Abstract

A variable capacitance device comprising, in a semiconductor layer formed on a substrate via an buried oxide film: an n− region 132 formed in the shape of a ring and containing an n-type dopant; an anode 133 adjoined to the outer periphery of the n− region 132, the anode 133 being formed in the shape of a ring and containing a p-type dopant; and a cathode 131 adjoined to the inner periphery of the n− region 132, the third region containing an n-type dopant, wherein the dopant concentration in the n− region 132 is lower than that in each of the anode 133 and the cathode 131.

1. A process for manufacturing a variable capacitance device comprising the steps of;
 forming a first region in a semiconductor layer formed on a substrate via an insulating layer, the first region containing a first conductivity type dopant;  
 forming a second region in a portion of the first region, the second region containing a second conductivity type dopant at a higher dopant concentration than that of the first region; and  
 forming a third region in a portion of the first region and apart from the second region, the third region containing a first conductivity type dopant at a higher dopant concentration than that of the first region, the contact area between the third region and the first region being smaller than that between the first region and the second region,  
 wherein the process further comprises the steps of:  
 forming, prior to the formation of the first region, a device isolation region in the semiconductor layer, the device isolation region isolating a first semiconductor-device-forming section for forming the variable capacitance device from each of a second semiconductor-device-forming section and a third semiconductor-device-forming section;  
 forming, in the step of forming the first region, a fourth region in the second semiconductor-device-forming section, the fourth region containing the same conductivity type dopant as the first region;  
 forming a fifth region in the third semiconductor-device-forming section, the fifth region containing a second conductivity type dopant at a lower dopant concentration than that of the second region;  
 forming a gate electrode on each of the fourth and fifth regions;  
 forming, in the step of forming the second region, a sixth region in the fourth region by using the gate electrode as a mask, the sixth region containing the same conductivity type dopant as the second region; and  
 forming, in the step of forming the third region, a seventh region in the fifth region by using the gate electrode as a mask, the seventh region containing the same conductivity type dopant as the third region.  
 
   
   
     2. A process for manufacturing a variable capacitance device according to  claim 1 ,
 wherein the second region is formed in the inner periphery portion of the first region, and the third region is formed in the center of the first region and apart from the second region.  
 
   
   
     3. A process for manufacturing a variable capacitance device according to  claim 1 ,
 wherein the second region is formed at one end of the first region, and the third region is formed at the other end of the first region.  
 
   
   
     4. A process for manufacturing a variable capacitance device according to  claim 3 ,
 wherein the second region and the third region are located so as to be opposed to each other across the first region, and  
 wherein the first region has an area in which the distance between the two side edges shortens gradually from the second region side toward the third region side.  
 
   
   
     5. A process for manufacturing a variable capacitance device according to  claim 1 , further comprising the step of, after masking the first region, siliciding the surface layers of the second and third regions.