Delay locked-loop circuit for reducing load of variable delay unit at high-frequency operation and locking external clock signal stably

Abstract

Disclosed is a delay locked-loop circuit comprising a phase detector for detecting a phase difference between an external clock signal and an internal clock signal, a delay unit controller for generating a control signal in response to output of the phase detector, and a variable delay unit for delaying the external clock in response to the control signal to synchronize the internal clock with the external clock, the variable delay unit comprising a first group of delay cells used at or above a predetermined frequency, a second group of delay cells used with the first group of delay cells at or below a predetermined frequency, switch transistors for connecting/disconnecting the first group of delay cells and the second group of delay cells to/from a first output line and a second output line of the variable delay unit, respectively, in response to the control signal, and a switch for connecting/disconnecting the first output line to/from the second output line in response to a delay use signal representing the use of one of the delay cells in the first group.

1. A delay locked-loop circuit comprising:
 a phase detector for detecting a phase difference between an external clock signal and an internal clock signal;  
 a delay unit controller for generating a control signal in response to output of the phase detector; and  
 a variable delay unit for delaying the external clock in response to the control signal to synchronize the internal clock with the external clock, the variable delay unit comprising:  
 a first group of delay cells used at or above a predetermined frequency;  
 a second group of delay cells used with the first group of delay cells below the predetermined frequency;  
 switch transistors for connecting/disconnecting the first group of delay cells and the second group of delay cells to/from a first output line and a second output line of the variable delay unit, respectively, in response to the control signal; and  
 a switch for connecting/disconnecting the first output line to/from the second output line in response to a delay use signal representing the use of one of the delay cells in the first group, wherein the delay use signal is a signal representing either the use of a last delay cell in the first group of delay cells or one of the remaining delay cells except the last delay cell.  
 
   
   
     2. The delay locked-loop circuit of  claim 1 , wherein the delay use signal is a signal representing the use of a delay cell that is disposed immediately before the switch. 
   
   
     3. A delay locked-loop circuit comprising:
 a phase detector for detecting a phase difference between an external clock and an internal clock;  
 a delay unit controller for generating a control signal in response to output of the phase detector; and  
 a variable delay unit for delaying the external clock in response to the control signal to synchronize the internal clock with the external clock, the variable delay unit comprising:  
 a first group of delay cells used at or above a predetermined frequency;  
 a second group of delay cells used with the first group of delay cells below the predetermined frequency;  
 switch transistors for connecting/disconnecting the first group of delay cells and the second group of delay cells to/from a first output line and a second output line of the variable delay unit, respectively, in response to the control signal;  
 a switch for connecting/disconnecting the first output line to/from the second output line, wherein the delay use signal is a signal representing either the use of a last delay cell in the first group of delay cells or one of the remaining delay cells except the last delay cell; and  
 a control circuit for controlling the turn-on/turn-off of the switch in response to a delay use signal representing the use of one of the delay cells in the first group and a reset signal.  
 
   
   
     4. The delay locked-loop circuit of  claim 3 , wherein the variable delay unit further comprises a reset circuit for generating the reset signal in response to an external reset command, an UP signal representing an increase in the number of the delay cells used, or a DOWN signal representing a decrease in the number of the delay cells used. 
   
   
     5. The delay locked-loop circuit of  claim 3 , wherein the variable delay unit further comprises a precharging circuit for precharging the second output line to a predetermined voltage level in response to a precharging signal output from the control circuit. 
   
   
     6. The delay locked-loop circuit of  claim 3 , wherein the control circuit comprises:
 a latch unit for setting an output terminal in response to the delay use signal and resetting the output terminal in response to the reset signal; and  
 a buffer for generating a switch control signal to control the switch.  
 
   
   
     7. The delay locked-loop circuit of  claim 4 , wherein the reset circuit comprises:
 an UP signal detecting circuit for counting the number of consecutive UP signals and activating output of the reset circuit if the counted number of consecutive UP signals is at or above a predetermined value;  
 a DOWN signal detecting circuit for counting the number of consecutive DOWN signals and activate output of the reset circuit if the counted number of consecutive DOWN signals is at or above a predetermined value; and  
 an OR circuit for generating the reset signal in response to the external reset command, output of the UP signal detecting circuit, or output of the DOWN signal detecting circuit.  
 
   
   
     8. The delay locked-loop circuit of  claim 7 , wherein the UP signal detecting circuit and the DOWN signal detecting circuit each comprise a counter. 
   
   
     9. The delay locked-loop circuit of  claim 5 , wherein the precharging circuit comprises a PMOS transistor. 
   
   
     10. The delay locked-loop circuit of  claim 3 , wherein the switch comprises a PMOS transistor. 
   
   
     11. A delay locked-loop circuit comprising:
 a phase detector for detecting a phase difference between an external clock and internal clock;  
 a delay unit controller for generating a control signal in response to output of the phase detector; and  
 a variable delay unit for delaying the external clock in response to the control signal to synchronize the internal clock with the external clock, the variable delay unit comprising:  
 a first group of delay cells used at or above a predetermined frequency;  
 a second group of delay cells used with the first group of delay cells below the predetermined frequency;  
 switch transistors for connecting/disconnecting the first group of delay cells and the second group of delay cells to/from a first output line and a second output line of the variable delay unit, respectively, in response to the control signal;  
 a switch for connecting/disconnecting the first output line to/from the second output line, wherein the second group of delay cells are used with either the use of a last delay cell in the first group of delay cells or at least one of the remaining delay cells except the last delay cell; and  
 a control circuit for controlling the turn-on/turn-off of the switch in response to delay variation signals representing variations in the number of delay cells used.  
 
   
   
     12. The delay locked-loop circuit of  claim 11 , wherein the variable delay unit further comprises a precharging circuit for precharging the second output line to a predetermined voltage level in response to a precharging signal output from the control circuit. 
   
   
     13. The delay locked-loop circuit of  claim 11 , wherein the control circuit comprises:
 a delay detection circuit for generating a variable voltage in response to an UP signal of the delay variation signals representing an increase in the number of the delay cells used, and in response to a DOWN signal of the delay variation signals representing a decrease in the number of the delay cells used;  
 a Schmitt trigger buffer for outputting the variable voltage as a first voltage if the variable voltage is at or above a first voltage level and as ground voltage if the variable voltage is at or below a second voltage, so as to generate the precharging signal; and  
 an inverter for inverting the precharging signal to generate a switch  
 control signal to control the switch.  
 
   
   
     14. The delay locked-loop circuit of  claim 12 , wherein the precharging circuit comprises a PMOS transistor. 
   
   
     15. The delay locked-loop circuit of  claim 13 , wherein the delay detection circuit comprises a charge pump. 
   
   
     16. The delay locked-loop circuit of  claim 13 , wherein the switch comprises a PMOS transistor. 
   
   
     17. A delay locked-loop circuit comprising:
 a phase detector for detecting a phase difference between an external clock signal and an internal clock signal;  
 a delay controller for generating a control signal in response to output of the phase detector; and  
 a variable delay for delaying the external clock in response to the control signal to synchronize the internal clock with the external clock, the variable delay having a first and second output lines; and  
 means for connecting/disconnecting a first group of delay cells used at or above a predetermined frequency and a second group of delay cells used with the first group of delay cells below the frequency to/from the first output line and the second output line, respectively, in response to the control signal, wherein the second group of delay cells are used with the use of at least one of the delay cells in the first group.  
 
   
   
     18. The delay locked-loop circuit of  claim 17 , further comprising second switch means for connecting/disconnecting the first output line to/from the second output line in response to a delay use signal representing the use of one of the delay cell means in the first group.