Method of manufacturing a semiconductor device

Abstract

Provided is a method of manufacturing a semiconductor device. In the method, an insulation spacer is formed thicker than a target thickness on sidewalls of a gate line formed on a semiconductor substrate. The thickness of the insulation spacer is adjusted by means of a wet etching process, so that aspect ratios of spaces between gate lines become smaller to control opening widths of junction areas. The method enhances fill-up characteristics of insulation layers between the gate lines, and improves the reliability of process and an electrical characteristic of device by controlling the opening widths of junction areas.

1. A method of manufacturing a semiconductor device, comprising the steps of:
 providing a semiconductor substrate; 
 forming gate lines on the semiconductor substrate, wherein a first space and a second space narrower than the first space are disposed between the gate lines; 
 forming a first junction area in the semiconductor substrate under the first space and forming a second junction area in the semiconductor substrate under the second space; 
 forming insulation spacers on sidewalls of the gate lines, wherein a portion of the first area is exposed and the second junction area is covered with the insulation spacers; 
 etching the insulation spacers, wherein an opening width of the first junction area is enlarged; and 
 forming an interlayer insulating layer on the overall structure including the gate lines. 
 
   
   
     2. The method of  claim 1 , wherein the insulation spacers are formed of a silicon oxide layer. 
   
   
     3. The method of  claim 1 , wherein the etching is carried out with a wet etching process. 
   
   
     4. The method of  claim 3 , wherein the wet etching process is performed with a diluted HF solution or a BOE solution. 
   
   
     5. The method of  claim 1 , wherein the etching is adjusted to make the insulation spacers equal to a target thickness based on an etching ratio of the insulation spacers. 
   
   
     6. The method of  claim 1 , further comprising, before forming the interlayer insulating layer, the step of forming a nitride layer on the overall structure including the gate lines. 
   
   
     7. The method of  claim 1 , wherein the interlayer insulating layer is formed of a BPSG. 
   
   
     8. The method of  claim 7 , wherein the BPSG contains 4.5 wt % boron and 4.0 wt % phosphorous. 
   
   
     9. The method of  claim 1 , further comprising, after forming the interlayer insulating layer, the step of carrying out a rapid thermal process to increase flexibility of the interlayer insulating layer.