US7061013B2ExpiredUtilityA1

Phase change storage cells for memory devices, memory devices having phase change storage cells and methods of forming the same

Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Mar 4, 2003Filed: Feb 26, 2004Granted: Jun 13, 2006
Est. expiryMar 4, 2023(expired)· nominal 20-yr term from priority
Inventors:Horii Hideki
G11C 13/0004H10N 70/8828H10N 70/8825H10N 70/8413H10N 70/826H10N 70/231H10N 70/063H10N 70/041H10N 70/026H10N 70/023H10D 84/00
81
PatentIndex Score
23
Cited by
6
References
19
Claims

Abstract

Storage cells for a phase change memory device and phase change memory devices are provided that include a first phase change material pattern and a first high-resist phase change material pattern on the first phase change material pattern. The first high-resist phase change material pattern has a higher resistance than the first phase change material pattern. Methods of fabricating such storage cells and/or memory devices are also provided.

Claims

exact text as granted — not AI-modified
1. A storage cell for a phase change memory device comprising:
 a first phase change material pattern; 
 a first high-resist phase change material pattern on the first phase change material pattern, the first high-resist phase change material pattern having a higher resistance than the first phase change material pattern; and 
 a second phase change material pattern on the first high-resist phase change material pattern such that the first high-resist phase change material pattern is interposed between the first and second phase change material patterns. 
 
     
     
       2. The storage cell of  claim 1 , wherein the first and second phase change material patterns and the first high-resist phase change material pattern are crystalline. 
     
     
       3. The storage cell of  claim 1 , wherein the first phase change material pattern is made of a material comprising tellurium (Te) and/or selenium (Se). 
     
     
       4. The storage cell of  claim 1 , wherein the first high-resist phase change material pattern comprises oxidized phase change material and/or nitrified phase change material. 
     
     
       5. The storage cell of  claim 1 , the first high-resist phase change material pattern comprises oxidized phase change material and wherein the oxidized phase change material contains tellurium (Te) and/or selenium (Se) and oxygen (O). 
     
     
       6. The storage cell of  claim 1 , wherein the first high-resist phase change material pattern comprises nitrified phase change material and wherein the nitrified phase change material contains tellurium (Te) and/or selenium (Se) and nitrogen (N). 
     
     
       7. The storage cell of  claim 1 , further comprising a barrier pattern on one of the first and second phase change material patterns and opposite the first high-resist phase change material pattern, the barrier pattern comprising a conductive layer. 
     
     
       8. A storage cell for a phase change memory device comprising:
 a first phase change material pattern; 
 a first high-resist phase change material pattern on the first phase change material pattern, the first high-resist phase change material pattern having a higher resistance than the first phase change material pattern; 
 a lower interlayer dielectric on a semiconductor substrate, wherein the first phase change material pattern is on the lower interlayer dielectric; 
 a lower plug configured to connect a predetermined region of the semiconductor substrate to the first phase change material pattern through the lower interlayer dielectric; 
 an upper interlayer dielectric on the lower interlayer dielectric, the first and second phase change material patterns and the first high-resist phase change material pattern; 
 an interconnection on the upper interlayer dielectric; and 
 an upper plug configured to connect the second phase change material pattern to the interconnection through the upper interlayer dielectric. 
 
     
     
       9. A phase change memory device incorporating the storage cell of  claim 1 . 
     
     
       10. A phase change memory device comprising:
 a lower interlayer dielectric on a semiconductor substrate; 
 a plurality of phase change material patterns that are sequentially stacked on the lower interlayer dielectric; and 
 a plurality of high-resist phase change material patterns interposed between adjacent ones of the phase change material patterns, the high-resist phase change material patterns having a higher resistance than the phase change material patterns, 
 wherein the phase change material patterns and the high-resist phase change material patterns provide an information storage component. 
 
     
     
       11. The phase change memory device of  claim 10 , wherein the phase change material patterns and the high-resist phase change material patterns are crystalline. 
     
     
       12. The phase change memory device of  claim 10 , wherein the phase change material patterns comprise tellurium (Te) and/or selenium (Se). 
     
     
       13. The phase change memory device of  claim 10 , wherein the high-resist phase change material patterns comprise oxidized phase change material and/or nitrified phase change material. 
     
     
       14. The phase change memory device of  claim 10 , wherein the high-resist phase change material patterns comprise oxidized phase change material and wherein the oxidized phase change material comprises tellurium (Te) and/or selenium (Se) and oxygen (O). 
     
     
       15. The phase change memory device of  claim 10 , wherein the high-resist phase change material patterns comprise nitrified phase change material and wherein the nitrified phase change material comprises tellurium (Te) and/or selenium (Se) and nitrogen (N). 
     
     
       16. The phase change memory device of  claim 10 , wherein opposing sides of the information storage component are composed of the phase change material patterns. 
     
     
       17. The phase change memory device of  claim 10 , further comprising a conductive layer on the information storage component to provide a barrier pattern on the information storage component. 
     
     
       18. The phase change memory device of  claim 10 , further comprising:
 a lower plug connected to a predetermined region of the semiconductor substrate and the information storage component through the lower interlayer dielectric; 
 an upper interlayer dielectric on the lower interlayer dielectric and the information storage component; 
 an interconnection the upper interlayer dielectric; and 
 an upper plug connected to the information storage component and the interconnection through the upper interlayer dielectric. 
 
     
     
       19. An information storage component of a phase change memory device comprising:
 a plurality of high-resist phase change material patterns interposed between adjacent lower resist phase change material patterns to provide a crystalline-state information storage component configured to change phase of only a portion of the plurality of high-resist phase change material patterns and adjacent lower resist phase change material patterns during heating/cooling.

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