Non-volatile memory and method for fabricating the same

Abstract

A non-volatile memory is provided. The memory comprises a substrate, a dielectric layer, a conductive layer, an isolation layer, a buried bit line, a tunneling dielectric layer, a charge trapping layer, a barrier dielectric layer and a word line. Wherein, the dielectric layer is disposed on the substrate. The conductive layer is disposed on the dielectric layer. The isolation layer is disposed on the substrate and adjacent to the dielectric layer and the conductive layer. The buried bit line is disposed in the substrate and underneath the isolation layer. The tunneling dielectric layer is disposed on both the substrate and the sidewalls of the conductive layer and the isolation layer. The charge trapping layer is disposed on the tunneling dielectric layer and the barrier dielectric layer is disposed on the charge trapping layer. The word line is disposed on the substrate, crisscrossing with the buried bit line.

1. A method for fabricating a non-volatile memory, the method comprising:
 providing a substrate, and sequentially forming a dielectric layer, a conductive layer, and a mask layer on the substrate; 
 pattering the mask layer, the conductive layer, and the dielectric layer to form a plurality of first openings exposing the substrate; 
 forming a buried bit line in the substrate at the bottom of each first opening; 
 forming an isolation layer in the first openings on the substrate; 
 removing part of the isolation layer, and forming a plurality of second openings by using the remained isolation layers as a mask; 
 removing the isolation layers covered on the mask layer and the mask layer; 
 forming a tunneling dielectric layer, a charge trapping layer, and a barrier dielectric layer sequentially on the substrate, so as to jointly cover the second openings, the isolation layer and the conductive layer; 
 filling a material layer into the second openings; 
 removing parts of the tunneling dielectric layer, the charge trapping layer, and the barrier dielectric layer not covered by the material layer; 
 removing the material layer; and 
 forming a word line on the substrate. 
 
   
   
     2. The method for fabricating the non-volatile memory of  claim 1 , wherein the method for forming the isolation layer comprises a high density plasma chemical vapor deposition (HDP-CVD) process. 
   
   
     3. The method for fabricating the non-volatile memory of  claim 1 , wherein the isolation layer can be made of silicon oxide, nitride, or SiOxNy. 
   
   
     4. The method for fabricating the non-volatile memory of  claim 1 , wherein at the step of removing part of the isolation layer, further comprises remaining a plurality of angled isolation layers on the mask layer. 
   
   
     5. The method for fabricating the non-volatile memory of  claim 4 , wherein a bottom width of each of the angled isolation layers is less than a width of the mask layer located below it. 
   
   
     6. The method for fabricating the non-volatile memory of  claim 1 , wherein the method for forming the second openings comprises an etching process. 
   
   
     7. The method for fabricating the non-volatile memory of  claim 1 , wherein the mask layer can be made of nitride. 
   
   
     8. The method for fabricating the non-volatile memory of  claim 1 , wherein the dielectric layer can be made of silicon oxide. 
   
   
     9. The method for fabricating the non-volatile memory of  claim 1 , wherein the method for forming the conductive layer and the mask layer comprises a chemical vapor deposition (CVD) process. 
   
   
     10. The method for fabricating the non-volatile memory of  claim 1 , wherein the method for forming the buried bit line in the substrate at the bottom of each of the first openings comprises an ion implanting process. 
   
   
     11. The method for fabricating the non-volatile memory of  claim 1 , wherein the method for removing the mask layer and the isolation layers covered on the mask layer comprises an etching process or a lift off process. 
   
   
     12. The method for fabricating the non-volatile memory of  claim 1 , wherein the method for filling the material layer into the second openings comprises a spin-on coating process. 
   
   
     13. The method for fabricating the non-volatile memory of  claim 1 , wherein the material layer can be made of a polymer material or a photoresistive material. 
   
   
     14. The method for fabricating the non-volatile memory of  claim 1 , wherein the method for removing parts of the tunneling dielectric layer, the charge trapping layer, and the barrier dielectric layer not covered by the material layer comprises an etching process. 
   
   
     15. The method for fabricating the non-volatile memory of  claim 1 , wherein the method for removing the material layer comprises an etching process. 
   
   
     16. The method for fabricating the non-volatile memory of  claim 1 , wherein the word line comprises a mixed polysilicon layer. 
   
   
     17. The method for fabricating the non-volatile memory of  claim 1 , wherein the method for forming the word line on the substrate comprises a chemical vapor deposition (CVD) process.