In-line voltage contrast determination of tunnel oxide weakness in integrated circuit technology development

Abstract

A method for determination of tunnel oxide weakness is provided. A tunnel oxide layer is formed on a semiconductor wafer. At least one poly gate is formed on the tunnel oxide layer in a flash memory region of the semiconductor wafer. At least one poly island, which is substantially larger than the poly gate, is formed on the tunnel oxide layer in a voltage contrast cell region of the semiconductor wafer. The poly island and the tunnel oxide layer therebeneath form a voltage contrast tunnel oxide cell. A voltage contrast measurement is performed on the voltage contrast tunnel oxide cell. The voltage contrast measurement is then compared with prior such voltage contrast measurements on other such voltage contrast tunnel oxide cells. The tunnel oxide weakness of the tunnel oxide layer is then determined from the voltage contrast measurement comparisons.

1. A method for determination of tunnel oxide weakness, comprising:
 forming a tunnel oxide layer on a semiconductor wafer; 
 forming at least one poly gate on the tunnel oxide layer in a flash memory region of the semiconductor wafer; 
 forming at least one poly island on the tunnel oxide layer in a voltage contrast cell region of the semiconductor wafer, the poly island being substantially larger than the poly gate, and the poly island and the tunnel oxide layer therebeneath forming a voltage contrast tunnel oxide cell; 
 performing a voltage contrast measurement on the voltage contrast tunnel oxide cell; 
 comparing the voltage contrast measurement with prior such voltage contrast measurements on other such voltage contrast tunnel oxide cells; and 
 determining the tunnel oxide weakness of the tunnel oxide layer from the voltage contrast measurement comparisons. 
 
   
   
     2. The method of  claim 1  wherein performing a voltage contrast measurement further comprises causing a constant standard testing current to flow through the voltage contrast tunnel oxide cell. 
   
   
     3. The method of  claim 1  further comprising accumulating a library of such voltage contrast measurements. 
   
   
     4. The method of  claim 1  further comprising depicting locations on a bitmap that correlate to the tunnel oxide defect locations on the semiconductor wafer. 
   
   
     5. The method of  claim 1  further comprising determining whether to continue or discontinue manufacturing of the semiconductor wafer as a function of the extent of tunnel oxide weakness detected by the voltage contrast tunnel oxide cell measurement. 
   
   
     6. A method for determination of tunnel oxide weakness, comprising:
 forming a tunnel oxide layer on a semiconductor wafer; 
 forming at least one poly gate on the tunnel oxide layer in a flash memory region of the semiconductor wafer; 
 forming at least one poly island on the tunnel oxide layer in a voltage contrast cell region of the semiconductor wafer, the poly island being substantially larger than the poly gate, and the poly island and the tunnel oxide layer therebeneath forming a voltage contrast tunnel oxide cell; 
 performing a voltage contrast measurement on the voltage contrast tunnel oxide cell in a tester; 
 generating and extracting test results from the tester; 
 comparing the voltage contrast measurement with prior such voltage contrast measurements on other such voltage contrast tunnel oxide cells in an analysis block; and 
 determining the tunnel oxide weakness of the tunnel oxide layer from the voltage contrast measurement comparisons. 
 
   
   
     7. The method of  claim 6  wherein performing a voltage contrast measurement further comprises causing a constant standard testing current to flow through the voltage contrast tunnel oxide cell. 
   
   
     8. The method of  claim 6  further comprising accumulating a library of such voltage contrast measurements. 
   
   
     9. The method of  claim 6  further comprising depicting locations on a bitmap that correlate to the tunnel oxide defect locations on the semiconductor wafer. 
   
   
     10. The method of  claim 6  further comprising determining whether to continue or discontinue manufacturing of the semiconductor wafer as a function of the extent of tunnel oxide weakness detected by the voltage contrast tunnel oxide cell measurement. 
   
   
     11. A system for determination of tunnel oxide weakness, comprising:
 a semiconductor wafer having at least one flash memory region and at least one voltage contrast cell region; 
 a tunnel oxide layer on the semiconductor wafer; 
 at least one poly gate on the tunnel oxide layer in a flash memory region of the semiconductor wafer; 
 at least one poly island on the tunnel oxide layer in a voltage contrast cell region of the semiconductor wafer, the poly island being substantially larger than the poly gate, and the poly island and the tunnel oxide layer therebeneath forming a voltage contrast tunnel oxide cell; 
 means for performing a voltage contrast measurement on the voltage contrast tunnel oxide cell; 
 means for comparing the voltage contrast measurement with prior such voltage contrast measurements on other such voltage contrast tunnel oxide cells; and 
 means for determining the tunnel oxide weakness of the tunnel oxide layer from the voltage contrast measurement comparisons. 
 
   
   
     12. The system of  claim 11  wherein the means for performing a voltage contrast measurement further comprises means for causing a constant standard testing current to flow through the voltage contrast tunnel oxide cell. 
   
   
     13. The system of  claim 11  further comprising a library of such voltage contrast measurements. 
   
   
     14. The system of  claim 11  further comprising a bitmap that depicts locations that correlate to the tunnel oxide defect locations on the semiconductor wafer. 
   
   
     15. The system of  claim 11  further comprising means for determining whether to continue or discontinue manufacturing of the semiconductor wafer as a function of the extent of tunnel oxide weakness detected by the voltage contrast tunnel oxide cell measurement. 
   
   
     16. A system for determination of tunnel oxide weakness, comprising:
 a semiconductor wafer having at least one flash memory region and at least one voltage contrast cell region; 
 a tunnel oxide layer on the semiconductor wafer; 
 at least one poly gate on the tunnel oxide layer in a flash memory region of the semiconductor wafer; 
 at least one poly island on the tunnel oxide layer in a voltage contrast cell region of the semiconductor wafer, the poly island being substantially larger than the poly gate, and the poly island and the tunnel oxide layer therebeneath forming a voltage contrast tunnel oxide cell; 
 means for performing a voltage contrast measurement on the voltage contrast tunnel oxide cell in a tester; 
 means for generating and extracting test results from the tester; 
 means for comparing the voltage contrast measurement with prior such voltage contrast measurements on other such voltage contrast tunnel oxide cells in an analysis block; and 
 means for determining the tunnel oxide weakness of the tunnel oxide layer from the voltage contrast measurement comparisons. 
 
   
   
     17. The system of  claim 16  wherein the means for performing a voltage contrast measurement further comprises means for causing a constant standard testing current to flow through the voltage contrast tunnel oxide cell. 
   
   
     18. The system of  claim 16  further comprising a library of such voltage contrast measurements. 
   
   
     19. The system of  claim 16  further comprising a bitmap that depicts locations that correlate to the tunnel oxide defect locations on the semiconductor wafer. 
   
   
     20. The system of  claim 16  further comprising means for determining whether to continue or discontinue manufacturing of the semiconductor wafer as a function of the extent of tunnel oxide weakness detected by the voltage contrast tunnel oxide cell measurement.