Multiple data path memories and systems

Abstract

The invention describes and provides multiple data path memories and systems utilizing such memories. Enhanced data throughput and bandwidth, while substantially simultaneously providing improved bus utilization, are some of the benefits. In peer-to-peer connected systems, multiple bank/access block/sector/sub-array with random data throughput can also be realized. A memory including a plurality of independently accessible memory banks, a READ BUS for selectively reading to a selected on of the memory banks, and a WRITE BUS independent of the READ BUS for selectively writing to a selected one of the memory banks, is described.

1. A memory integrated circuit comprising:
 a plurality of independently accessible memory banks, wherein each of said plurality of independently accessible memory banks is associated with a sense amplifier, wherein said plurality of independently accessible memory banks are sequentially cycled for one of a READ and a WRITE at a system clock frequency; 
 a read bus connected to each of said sense amplifiers associated with each of said plurality of independently accessible memory banks, wherein said read bus is configured to select one of said plurality of independently accessible memory banks to read; 
 a write bus connected to each of said sense amplifiers associated with each of said plurality of independently accessible memory banks, wherein said write bus is configured to select one of said plurality of independently accessible memory banks to write, wherein said write bus is independent of said read bus; 
 wherein the read bus and the write bus further operate to permit concurrent selective read and write functionality; and 
 wherein a first bank of said plurality of independently accessible memory banks is read from and a second bank of said plurality of independently accessible memory banks is written to simultaneously. 
 
     
     
       2. A memory system as in  claim 1 , wherein the memory integrated circuit comprises a plurality of memory cells wherein the plurality of memory cells require periodic data refresh. 
     
     
       3. A memory system as in  claim 1 , wherein the memory integrated circuit comprises static memory cells, wherein the static memory cells do not require periodic data refresh. 
     
     
       4. A memory system as in  claim 1 , wherein the memory integrated circuit comprises a plurality of nonvolatile memory cells. 
     
     
       5. A memory system as in  claim 1 , wherein the memory integrated circuit comprises a combination of dynamic, static and nonvolatile memory cells. 
     
     
       6. A memory system as in  claim 1 , wherein the memory integrated circuit further comprises a SIP (System In Package). 
     
     
       7. A memory system as in  claim 1 , wherein the memory integrated circuit further comprises a SOC (System On Chip). 
     
     
       8. A memory system as in  claim 1 , wherein the memory integrated circuit permits operation in a shared common bus environment. 
     
     
       9. A memory system as in  claim 1 , wherein the memory integrated circuit permits operation in a peer-to-peer environment. 
     
     
       10. A memory system as in  claim 1 , wherein the memory integrated circuit further comprises rail-to-rail electric signaling. 
     
     
       11. A memory system as in  claim 1 , wherein the memory integrated circuit single ended electrical signaling. 
     
     
       12. A memory system as in  claim 1 , wherein the memory integrated circuit operates synchronously. 
     
     
       13. A memory system as in  claim 1 , wherein the memory integrated circuit operates a synchronously.