Delay locked loop and its control method for correcting a duty ratio of a clock signal

Abstract

A delay locked loop (DLL) capable of correcting a duty ratio including: a clock buffer for receiving an external clock signal and an inverted external clock signal to generate a rising edge clock signal; a delay unit for delaying the rising edge clock signal based on a first comparison signal in order to generate a first internal clock signal, a second internal clock signal, a first delay locking signal and a second delay locking signal; a duty correction unit for receiving the first and the second internal clock signals and the first and the second delay locking signals to generate a mixed clock signal; a delay model unit for delaying the mixed clock signal to generate a feed-backed clock signal; and a first phase detector for receiving the external clock signal and the feed-backed clock signal to generate the first comparison signal.

1. A delay locked loop (DLL) capable of correcting a duty ratio of a clock signal comprising:
 a clock buffer for receiving an external clock signal and an inverted external clock signal to generate a rising edge clock signal by buffering the external clock signal and the inverted external clock signal; 
 a delay means for delaying the rising edge clock signal based on a first comparison signal in order to generate a first internal clock signal and a second internal clock signal and generating a first delay locking signal and a second delay locking signal based on the first comparison signal; 
 a duty correction means for receiving the first and the second internal clock signals and the first and the second delay locking signals to generate a mixed clock signal which is duty corrected by mixing phases of the first and the second internal clock signals applying a first weight and a second weight to the first and the second internal clock signals respectively; 
 a delay model unit for delaying the mixed clock signal for a predetermined delay time to generate a feed-backed clock signal; and 
 a first phase detector for receiving the external clock signal and the feed-backed clock signal to generate the first comparison signal by comparing phases of the external clock signal and the feed-backed clock signal. 
 
   
   
     2. The DLL as recited in  claim 1 , wherein the delay means includes:
 a delay line controller which receives the first comparison signal and the first and the second delay locking signals to generate a first delay line control signal and a second delay line control signal; 
 a first delay line which receives the rising edge clock signal and delays the rising edge clock signal based on the first delay line control signal in order to generate the first internal clock signal; 
 a second delay line which receives an inverted signal of the first internal clock signal and delays the inverted signal based on the second delay line control signal in order to generate the second internal clock signal; and 
 a locking detector which receives the first comparison signal and determines whether or not the first and the second delay lines are delay locked based on the first comparison signal in order to generate the first and the second delay locking signal. 
 
   
   
     3. The DLL as recited in  claim 2 , wherein the duty correction means includes:
 a second phase detector which receives inverted signals of the first and the second internal clock signals and determines which one of falling edges of the received signals leads the other in order to generate a second comparison signal; 
 a weight controller which receives the second comparison signal and the first and the second delay locking signals in order to generate a weight value; and 
 a phase mixer which receives the first and the second internal clock signals to generate the mixed clock signals by mixing phases applying the weight value to the second internal clock signal and a second weight value to the first internal clock signal, wherein the second weight value is a value of subtracting the weight value from 1. 
 
   
   
     4. The DLL as recited in  claim 3 , wherein the weight value includes a first selection signal, a second selection signal, a first selection bar signal and a second selection bar signal. 
   
   
     5. The DLL as recited in  claim 4 , wherein the weight controller makes the first and the second selection signals be in a second logic level and makes the first and the second selection bar signals be in a first logic level when the first and the second delay locking signals are in a first logic level. 
   
   
     6. The DLL as recited in  claim 4 , wherein the weight controller makes the first and the second selection signals be in a first logic level and makes the first and the second selection bar signals be in a second logic level when the first delay locking signal is in a second logic level and the second delay locking signal is in a first logic level. 
   
   
     7. The DLL as recited in  claim 4 , wherein the weight controller makes the first selection signal and the second selection bar signal be in a first logic level and makes the first selection bar signal and the second selection signal be in a first logic level when the first and the second delay locking signals and the second comparison signal are in a second logic level. 
   
   
     8. The DLL as recited in  claim 4 , wherein the weight controller makes the first selection signal and the second selection bar signal be in a second logic level and makes the first selection bar signal and the second selection signal be in a first logic level when the first and the second delay locking signals are in a second logic level and the second comparison signal is in a first logic level. 
   
   
     9. The DLL as recited in  claim 4 , wherein the phase mixer includes:
 a first phase selector for correcting a phase of the first internal clock signal based on the first and the second selection signals and the first and the second selection bar signals; and 
 a second phase selector for correcting a phase of the second internal clock signal based on the first and the second selection signals and the first and the second selection bar signals. 
 
   
   
     10. The DLL as recited in  claim 9 , wherein the first phase selector includes a plurality of unit phase mixers each of which receives the first and the second selection signals or the first and the second selection bar signals. 
   
   
     11. The DLL as recited in  claim 10 , wherein each of the plurality of unit phase mixers includes:
 a first PMOS transistor whose source and gate are respectively connected to a power supply voltage and one of the first and the second internal clock signals; 
 a second PMOS transistor whose source and gate are respectively connected to a drain of the first PMOS transistor and one of the first and the second selection signals and the first and the second selection bar signals; 
 a first NMOS transistor whose source and gate are respectively connected to a ground and one of the first and the second internal clock signals; and 
 a second NMOS transistor whose drain and gate are respectively connected to a grain of the second PMOS transistor and one of the first and the second selection signals and the first and the second selection bar signals. 
 
   
   
     12. A delay locked loop (DLL) capable of correcting a duty ratio of a clock signal comprising:
 a clock buffer for receiving an external clock signal and an inverted external clock signal to generate a rising edge clock signal by buffering the external clock signal and the inverted external clock signal; 
 a delay means for delaying the rising edge clock signal based on a first comparison signal in order to generate a first internal clock signal and a second internal clock signal and generating a first delay locking signal and a second delay locking signal based on the first comparison signal; 
 a duty correction means for receiving the first and the second internal clock signals and the first and the second delay locking signals to generate a mixed clock signal which is duty corrected by mixing phases of the first and the second internal clock signals applying a first weight and a second weight to the first and the second internal clock signals respectively; 
 a delay model unit for delaying the mixed clock signal for a predetermined delay time to generate a feed-backed clock signal; and 
 a first phase detector which receives the rising edge clock signal and the feed-backed clock signal to generate the first comparison signal by comparing phases of the rising edge clock signal and the feed-backed clock signal. 
 
   
   
     13. The DLL as recited in  claim 12 , wherein the delay means includes:
 a delay line controller which receives the first comparison signal and the first and the second delay locking signals to generate a first delay line control signal and a second delay line control signal; 
 a first delay line which receives the rising edge clock signal and delays the rising edge clock signal based on the first delay line control signal in order to generate the first internal clock signal; 
 a second delay line which receives an inverted signal of the first internal clock signal and delays the inverted signal based on the second delay line control signal in order to generate the second internal clock signal; and 
 a locking detector which receives the first comparison signal and determines whether or not the first and the second delay lines are delay locked based on the first comparison signal in order to generate the first and the second delay locking signal. 
 
   
   
     14. The DLL as recited in  claim 13 , wherein the duty correction means includes:
 a second phase detector which receives inverted signals of the first and the second internal clock signals and determines which one of falling edges of the received signals leads the other in order to generate a second comparison signal; 
 a weight controller which receives the second comparison signal and the first and the second delay locking signals in order to generate a weight value; and 
 a phase mixer which receives the first and the second internal clock signals to generate the mixed clock signals by mixing phases applying the weight value to the second internal clock signal and a second weight value to the first internal clock signal, wherein the second weight value is a value of subtracting the weight value from 1. 
 
   
   
     15. The DLL as recited in  claim 14 , wherein the weight value includes a first selection signal, a second selection signal, a first selection bar signal and a second selection bar signal. 
   
   
     16. The DLL as recited in  claim 15 , wherein the weight controller makes the first and the second selection signals be in a second logic level and makes the first and the second selection bar signals be in a first logic level when the first and the second delay locking signals are in a first logic level. 
   
   
     17. The DLL as recited in  claim 15 , wherein the weight controller makes the first and the second selection signals be in a first logic level and makes the first and the second selection bar signals be in a second logic level when the first delay locking signal is in a second logic level and the second delay locking signal is in a first logic level. 
   
   
     18. The DLL as recited in  claim 15 , wherein the weight controller makes the first selection signal and the second selection bar signal be in a first logic level and makes the first selection bar signal and the second selection signal be in a first logic level when the first and the second delay locking signals and the second comparison signal are in a second logic level. 
   
   
     19. The DLL as recited in  claim 15 , wherein the weight controller makes the first selection signal and the second selection bar signal be in a second logic level and makes the first selection bar signal and the second selection signal be in a first logic level when the first and the second delay locking signals are in a second logic level and the second comparison signal is in a first logic level. 
   
   
     20. The DLL as recited in  claim 15 , wherein the phase mixer includes:
 a first phase selector for correcting a phase of the first internal clock signal based on the first and the second selection signals and the first and the second selection bar signals; and 
 a second phase selector for correcting a phase of the second internal clock signal based on the first and the second selection signals and the first and the second selection bar signals. 
 
   
   
     21. The DLL as recited in  claim 20 , wherein the first phase selector includes a plurality of unit phase mixers each of which receives the first and the second selection signals or the first and the second selection bar signals. 
   
   
     22. The DLL as recited in  claim 21 , wherein each of the plurality of unit phase mixers includes:
 a first PMOS transistor whose source and gate are respectively connected to a power supply voltage and one of the first and the second internal clock signals; 
 a second PMOS transistor whose source and gate are respectively connected to a drain of the first PMOS transistor and one of the first and the second selection signals and the first and the second selection bar signals; 
 a first NMOS transistor whose source and gate are respectively connected to a ground and one of the first and the second internal clock signals; and 
 a second NMOS transistor whose drain and gate are respectively connected to a grain of the second PMOS transistor and one of the first and the second selection signals and the first and the second selection bar signals. 
 
   
   
     23. A method for correcting a duty ratio of a clock signal in a DLL comprising steps of:
 a) initializing the DLL, which includes a first delay line and a second delay line connected in series for receiving an external clock signal, and enabling the first delay line for generating a first internal clock signal; 
 b) passing the first internal clock signal through a feed-back loop for generating a feed-backed clock signal and comparing the feed-backed clock signal with the external clock signal until rising edges of the external clock signal and the feed-backed clock signal are synchronized; 
 c) enabling the second delay line for generating a second internal clock signal if the rising edges of the external clock signal and the feed-backed clock signal are synchronized; 
 d) passing the second internal clock signal through the feed-back loop for generating the feed-backed clock signal and comparing the feed-backed clock signal with the external clock signal until rising edges of the external clock signal and the feed-backed clock signal are synchronized; and 
 e) performing a phase mixing operation on the first and second internal clocks if the rising edges of the external clock signal and the feed-backed clock signal are synchronized. 
 
   
   
     24. The method for correcting a duty ratio of a clock signal in a DLL as recited in  claim 23 , wherein the first internal clock signal is generated by buffering the external clock signal. 
   
   
     25. The method for correcting a duty ratio of a clock signal in a DLL as recited in  claim 23 , wherein the step of b) further includes a step of f) controlling a delay amount of the first delay line if the rising edges of the external clock signal and the feed-backed clock signal are not synchronized. 
   
   
     26. The method for correcting a duty ratio of a clock signal in a DLL as recited in  claim 23 , wherein the step of d) further includes a step of g) controlling a delay amount of the second delay line if the rising edges of the external clock signal and the feed-backed clock signal are not synchronized.