Set programming methods and write driver circuits for a phase-change memory array

Abstract

Exemplary embodiments of the present invention provide set programming methods and write driver circuits for a phase-change memory array. An exemplary embodiment of a set programming method may comprise applying a set current pulse to the phase-change cells, which may cause phase-change cells, which may be included within the phase-change memory array, to transition to the set resistance state. Exemplary embodiments of the set programming methods and/or write driver circuits may result in the phase-change cells to transition to the set resistance state.

1. A set programming method for a phase-change memory array having a plurality of phase-change cells that transition to a reset resistance state or a set resistance state in response to a current pulse applied thereto, comprising:
 transitioning phase-change cells to the set resistance state as a result of applying a set current pulse to the phase-change cells; wherein
 the set current pulse is generated based on a set voltage pulse having a plurality of stages in which a magnitude of voltage is gradually decreased, and 
 the set current pulse includes a plurality of stages in which a magnitude of the set current pulse is gradually decreased. 
 
 
     
     
       2. The set programming method of  claim 1 , wherein the plurality of stages of the set current pulse and the set voltage pulse each include at least a first through an nth stages, where n is greater than or equal to two. 
     
     
       3. The set programming method as claimed in  claim 2 , wherein the magnitude of the set current pulse of the first stage corresponds to a maximum current for transitioning a phase-change cell to the set resistance state. 
     
     
       4. The set programming method as claimed in  claim 2 , wherein the magnitude of the set current pulse of the first stage does not exceed a magnitude of current for heating the phase-change cells to their melting temperature. 
     
     
       5. The set programming method as claimed in  claim 1 , further including stages during which the magnitude of the set current pulse is zero. 
     
     
       6. The set programming method as claimed in  claim 1 , wherein the set current pulse of the plurality of stages are sequentially generated. 
     
     
       7. The set programming method as claimed in  claim 1 , wherein the plurality of stages of the set current pulse includes four stages. 
     
     
       8. A write driver circuit implementing the set programming method of  claim 1 . 
     
     
       9. A set programming method for a phase-change memory array having a plurality of phase-change cells that transition to a reset resistance state or a set resistance state in response to a current pulse applied thereto, comprising:
 applying a first current pulse with a magnitude to the phase-change cells such that the phase-change cells transition to the set resistance state; and 
 applying, sequentially, n additional current pulses, where n is greater than or equal to one, magnitudes of which are smaller than the magnitude of the first current pulse, to the phase-change cells; wherein
 the set current pulses are generated based on a set voltage pulse having first through nth stages, where n is greater than or equal to two and in which a magnitude of voltage is gradually decreased, and 
 the magnitudes of the second through nth current pulses are sequentially reduced. 
 
 
     
     
       10. The set programming method as claimed in  claim 9 , wherein the magnitude of current of the first current pulse corresponds to a maximum current for transitioning a phase-change cell to the set resistance state. 
     
     
       11. The set programming method as claimed in  claim 9 , wherein the magnitude of the first current pulse does not exceed a magnitude of current for heating the phase-change cells to their melting temperature. 
     
     
       12. The set programming method as claimed in  claim 9 , further including stages during which the magnitude of the set current pulse is zero. 
     
     
       13. The set programming method as claimed in  claim 9 , wherein the first through nth current pulses are sequentially generated. 
     
     
       14. The set programming method as claimed in  claim 8 , wherein the plurality of stages of the set current pulse includes four stages. 
     
     
       15. A write driver circuit implementing the set programming method of  claim 9 . 
     
     
       16. A write driver circuit of a phase-change memory array having a plurality of phase-change cells that transition to a reset resistance state or a set resistance state in response to a current pulse applied thereto, the write driver circuit comprising:
 a pulse generator adapted to generate a set voltage pulse having first through nth stages, where n is greater than or equal to two, in which a magnitude of voltage is gradually decreased; and 
 a current controller adapted to apply a set current pulse to the phase-change cells, wherein the set current pulse has a first through nth stages, where n is greater than or equal to two, in which a magnitude of current is gradually decreased based upon the set voltage pulse. 
 
     
     
       17. The write driver circuit as claimed in  claim 16 , wherein the current controller includes:
 a first transistor having a first terminal connected to a power supply voltage and a second terminal connected to the gate thereof; 
 a second transistor having a first terminal connected to the power supply voltage, a second terminal through which the set current pulse is output, and a gate connected to the gate of the first transistor; and 
 a control transistor having a first terminal connected to the second terminal of the first transistor and a second terminal connected to a ground voltage, wherein a degree to which the control transistor is turned on is determined by the set voltage pulse applied to the gate thereof. 
 
     
     
       18. The write driver circuit as claimed in  claim 16 , wherein the magnitude of the set voltage pulse of the first stage corresponds to a maximum voltage for a phase-change cell that requires a maximum current to transition to the set resistance state. 
     
     
       19. The write driver circuit as claimed in  claim 16 , wherein the magnitude of the set voltage pulse of the first stage does not exceed a voltage required to generate a set current pulse for heating the phase-change cells to their melting temperature. 
     
     
       20. The write driver circuit as claimed in  claim 16 , further including stages during which the magnitude of the set current pulse is zero. 
     
     
       21. The write driver circuit as claimed in  claim 16 , wherein the set voltage pulses of the first to nth stages are sequentially generated. 
     
     
       22. The write driver circuit as claimed in  claim 16 , wherein n is four. 
     
     
       23. A write driver circuit adapted to generate a plurality of set current pulses in response to a plurality of set voltage pulses during a plurality of stages wherein the magnitude of the set voltage pulses and set current pulses gradually decrease, and the set current pulses are applied to a plurality of phase-change memory cells such that the plurality of phase-change cells transition to a set state.