Forming a substantially planar upper surface at the outer edge of a semiconductor topography

Abstract

A method is provided for processing a semiconductor topography such that its upper surface is substantially planar, particularly including a region adjacent to an outer edge of a semiconductor topography. The method may include preferentially removing a portion of an upper layer of the topography in a region adjacent to an outer edge of the semiconductor topography. The region may extend greater than approximately 3 mm inward from the outer edge of the semiconductor topography. The method may also include polishing the semiconductor topography such that the upper surface of the semiconductor topography is substantially planar. Therefore, although a rate of polishing adjacent to an outer edge of the semiconductor topography may be slower than a rate of polishing adjacent to a center of the semiconductor topography, a thickness variation of the polished upper layer across the entirety of the semiconductor topography may be less than approximately 500 angstroms.

1. A semiconductor topography comprising an upper layer formed conformally upon a non-planar lower layer, wherein the upper layer is present across the entire topography, and an average thickness of the upper layer in a region adjacent to an outer edge of the semiconductor topography is approximately 5% to approximately 30% less than an average thickness of the upper layer in a region comprising a center of the topography. 
   
   
     2. The semiconductor topography of  claim 1 , wherein the region having a lower average thickness extends greater than approximately 3 mm laterally from the outer edge of the semiconductor topography. 
   
   
     3. The semiconductor topography of  claim 1 , wherein the lower layer comprises a plurality of spaced structures. 
   
   
     4. The semiconductor topography of  claim 3 , wherein the plurality of spaced structures comprise a polish stop material. 
   
   
     5. The semiconductor topography of  claim 3 , wherein one of the spaced structures is arranged within 4 mm from the outer edge. 
   
   
     6. The semiconductor topography of  claim 3 , wherein the plurality of spaced structures are selected from the group consisting of gate structures, contact structures, local interconnect structures, conductive plugs, shallow trench isolation structures, dielectric layers, and conductive layers.