Method and structure for fabricating non volatile memory arrays

Abstract

An MONOS integrated circuit device. The device has a semiconductor substrate comprising a silicon bearing material and a shallow trench isolation region formed within the substrate. A P-type well region is formed within the substrate and adjacent to the shallow trench isolation region. The first word gate comprising a first edge and a second edge. The first word gate comprises a first control gate coupled to the first edge and a second control gate coupled to the second edge. Preferably, the second word gate comprises a first edge and a second edge. The second word gate comprises a first control gate coupled to the first edge and a second control gate coupled to the second edge. A common buried bit line is formed within the P-type well region and between the second edge of the first word gate and the first edge of the second word gate. An HDP plasma dielectric is formed overlying the common buried bitline to a height within a vicinity of a first surface of the first word gate and a second surface of the second word gate. In a preferred embodiment, the device has a planarized surface formed from a portion of the HDP plasma dielectric, the first surface, and the second surface. A word line is overlying the planarized surface. The word line is coupled to the first word gate and the second word gate and is overlying the HDP plasma dielectric. The device has a refractory metal layer formed overlying the word line, a hard mask layer overlying the refractory metal layer, and a cap layer formed overlying the hard mask layer. The word line, refractory metal layer, hard mask layer, and cap layer form a planarized structure.

1. A method for forming a memory device, the method comprising a sequence of steps:
 providing a substrate comprising a surface region; 
 forming well structure within the substrate, the well structure including a cell well region for a plurality of cell regions and a peripheral well region for a peripheral region; 
 forming a gate dielectric layer overlying the surface region, the surface region extending over the cell well region and the peripheral well region; 
 forming polysilicon film overlying the gate dielectric layer overlying the well structure; 
 forming cap layer overlying the polysilicon film; 
 selectively removing a portion of the cap layer overlying the cell regions to expose the polysilicon film overlying the cell regions while maintaining the cap layer on the peripheral region; 
 forming a blanket nitride layer overlying the cap layer and exposed cell region; 
 forming a plurality of word gates by patterning the polysilicon film in the cell region while using a portion of the nitride layer as a hard mask while exposing a portion of the surface of the substrate between each of the word gates; 
 forming control gate channel implant; 
 forming an oxide-on-nitride-on oxide layer overlying the word gates and exposed portion of the surface of the substrate between each of the word gates; 
 forming a pair of polysilicon sidewall spacers on each word gate to form a pair of control gates while each pair of control gates is being isolated electrically from the word gate by a portion of the oxide-on-nitride-on-oxide layer, each of the control gates also being overlying a portion of the oxide-on-nitride-on oxide; 
 forming cell LDD structures for each of the control gates; 
 forming a buried bit line structure within a portion of the substrate for each of the LDD structures; 
 forming an interlayer dielectric overlying regions within each of the word gate structures; 
 protecting the cell regions; and 
 processing the peripheral region while maintaining the protection on the cell region. 
 
     
     
       2. The method of  claim 1  wherein the processing the peripheral region comprises:
 forming gate structures; 
 forming sidewall spacer structures on the gate structures; and 
 forming source/drain structures. 
 
     
     
       3. The method of  claim 1  wherein the forming the interlayer dielectric comprising depositing an HDP oxide layer to fill gaps between each of the word gates to form an uneven surface overlying the memory cell region. 
     
     
       4. The method of  claim 3  further comprising planarizing the uneven surface. 
     
     
       5. The method of  claim 1  wherein the protecting comprises applying a photomask layer over the memory cell region. 
     
     
       6. The method of  claim 1  wherein the gate dielectric layer is an oxide layer. 
     
     
       7. The method of  claim 1  wherein the blanket nitride layer is formed over an entirety of the cap layer and exposed cell region. 
     
     
       8. The method of  claim 1  wherein the buried bit line is provided using a diffusion or implantation process. 
     
     
       9. The method of  claim 1  wherein the protecting of the cell region is provided by a masking process. 
     
     
       10. The method of  claim 1  wherein the processing of the peripheral region comprises patterning and etching. 
     
     
       11. A method for forming integrated circuits, the method comprising:
 providing a substrate comprising a surface region; 
 forming a cell region and a peripheral region on the surface region of the substrate; 
 forming a gate dielectric layer overlying the cell region and the peripheral region; 
 forming a gate layer overlying the gate dielectric layer; 
 forming a protective layer overlying the peripheral region; 
 forming a plurality of memory cell devices in the memory cell region, each of the memory cell device including a word gate coupled to a pair of control gates, each of the word gates having a capping layer thereon, each of the control gates having a height lower than a surface of the capping layer, wherein the forming of the plurality of memory cell devices further including forming a control gate channel implant before forming the control gates and forming cell LDD structures for each of the control gates after forming the control gates; 
 forming an interlayer dielectric using high density plasma overlying an entirety of the surfaces including peripheral region and cell region to a height above the surface of the capping layer; 
 forming a protective layer overlying the interlayer dielectric layer portion overlying the cell region while exposing the peripheral region; 
 removing the exposed portion of the interlayer dielectric layer in the peripheral region; 
 performing a chemical mechanical polishing process to remove a portion of the interlayer dielectric layer overlying the cell region; 
 maintaining the chemical polishing process until the capping layer on each of the gates has been exposed; 
 performing a wet oxide etch to substantially remove oxide on the capping layer on each of the gates; 
 selectively removing the capping layer from each of the word gates to expose the word gates; and 
 forming a conductive layer overlying each of the word gates. 
 
     
     
       12. The method of  claim 11  wherein the capping layer comprises a silicon nitride layer. 
     
     
       13. The method of  claim 11  wherein the protective layer comprises a photoresist material. 
     
     
       14. The method of  claim 11  wherein the interlayer dielectric comprises HDP oxide. 
     
     
       15. The method of  claim 11  wherein each of the control gates comprises a separate memory device. 
     
     
       16. The method of  claim 11  wherein the recessed region is formed using selective etching of the interlayer dielectric layer. 
     
     
       17. The method of  claim 11  wherein each of the control gates is a spacer coupled to one of the word gates.