Digital duty cycle corrector

Abstract

A method for adjusting the relative phases of two signals includes receiving first and second signals, which may, for example, be derived from a differential clock signal. A duty cycle error between the first signal and the second signal is detected by comparing a phase component of the first signal with a phase component of the second signal. This duty cycle error can then be corrected by delaying the second signal by an amount based upon a result derived from the comparing.

1. A method of adjusting the relative phases of two signals, the method comprising:
 receiving a first signal and a second signal; 
 detecting a duty cycle error between the first signal and the second signal by comparing a phase component of the first signal with a phase component of the second signal, wherein detecting a duty cycle error comprises:
 delaying the first signal by a first amount to create a first delayed signal; 
 delaying the second signal by the first amount to create a second delayed signal; 
 comparing a phase of the first signal with a phase of the second delayed signal and providing a first output signal; and 
 comparing a phase of the second signal with a phase of the first delayed signal and providing a second output signal; and 
 
 correcting the duty cycle error by delaying the second signal by an amount of delay, the amount of delay being adjusted on the basis of a combination of the first output signal and the second output signal. 
 
   
   
     2. The method of  claim 1  wherein the step of receiving a first signal and a second signal comprises receiving a differential signal and deriving the first signal and the second signal from the differential signal. 
   
   
     3. The method of  claim 1  wherein the first signal is a complement of the second signal. 
   
   
     4. The method of  claim 1  and further comprising adjusting the first amount of delay based upon the first output signal and the second output signal. 
   
   
     5. The method of  claim 4  wherein the first amount of delay is adjusted until a rising edge of the first signal is aligned with a rising edge of the second delayed signal. 
   
   
     6. The method of  claim 1  wherein the first amount of delay is adjusted by a second amount so that the rising edge of the first signal is aligned with the rising edge of the second delayed signal and wherein the step of correcting the duty cycle error comprises delaying the second signal by an amount equal to about half of the second amount. 
   
   
     7. The method of  claim 1  wherein the first signal comprises a first clock signal and wherein the second signal comprises a second clock signal. 
   
   
     8. The method of  claim 7  wherein the step of receiving a first signal and a second signal comprises receiving a differential clock signal and deriving the first clock signal and the second clock signal from the differential clock signal. 
   
   
     9. A method of operating a semiconductor device, the method comprising:
 receiving a first signal; 
 receiving a second signal that is a complement of the first signal; 
 delaying the first signal by a first amount of delay to obtain a delayed version of the first signal, the first amount of delay being adjusted so that an edge of the delayed version of the first signal is aligned to an edge of the second signal; 
 delaying the second signal by the first amount of delay to obtain a delayed version of the second signal; and 
 delaying the second signal by a second amount of delay, the second amount of delay adjusted to create a selected duty cycle between the first signal and the second signal after the second signal has been delayed by the second amount of delay, 
 wherein the second amount of delay is adjusted on the basis of a combination of a first output signal and a second output signal, the first output signal being obtained by comparing a phase of the first signal with a phase of the second delayed signal and providing a first output signal, and the second output signal being obtained by comparing a phase of the second signal with a phase of the first delayed signal and providing the second output signal. 
 
   
   
     10. The method of  claim 9  wherein the first amount of delay is determined from the phase of the first signal and the phase of a second signal. 
   
   
     11. The method of  claim 10  wherein the first amount of delay is determined on the basis of a comparison of the phase of the first signal to the phase of the delayed version of the second signal. 
   
   
     12. The method of  claim 11  wherein the first amount of delay is also determined on the basis of a comparison of the phase of the second signal to the phase of the delayed version of the first signal. 
   
   
     13. The method of  claim 10  wherein the first amount of delay is determined on the basis of a comparison of the phase of the second signal to the phase of the delayed version of the first signal. 
   
   
     14. The method of  claim 9  wherein the first signal and the second signal are derived from a differential clock signal, the first signal being a complement of the second signal. 
   
   
     15. The method of  claim 14  wherein the semiconductor device comprises a double data rate synchronous dynamic random access memory, the method further comprising:
 outputting a first data bit synchronously with the first signal; and 
 outputting a second data bit synchronously with the second signal. 
 
   
   
     16. The method of  claim 15  wherein the step of outputting a first data bit comprises outputting the first bit of data synchronously with a rising edge of the first signal and wherein outputting a second data bit comprises outputting the second bit of data synchronously with a rising edge of the second signal. 
   
   
     17. A method of adjusting clock signals, the method comprising:
 receiving a differential clock; 
 generating a first input clock signal and a second input clock signal from the differential clock signal; 
 delaying the first input clock signal to derive a first output clock signal; 
 delaying the second input clock signal to derive a second output clock signal; 
 delaying the first output clock signal to derive a first delayed clock signal; 
 delaying the second output clock signal to derive a second delayed clock signal; 
 comparing a phase of the first output clock signal with a phase of the second delayed clock signal and providing a first output signal; 
 comparing a phase of the second output clock signal with a phase of the first delayed clock signal and providing a second output signal; and 
 adjusting the delay of the second input clock signal by a first amount and adjusting the delay of the first and second output clock signals by a second amount, the first amount and the second amount being set on the basis of a combination of the first output signal and the second output signal. 
 
   
   
     18. A phase adjustment circuit comprising:
 a first delay element having an input and an output; 
 a second delay element having an input and an output; 
 a third delay element having an input and an output, the input of the third delay element being coupled to the output of the first delay element; 
 a fourth delay element having an input and an output, the input of the fourth delay element being coupled to the output of the second delay element; 
 a first phase detector having a first input coupled to the output of the second delay element and a second input coupled to the output of the third delay element; 
 a second phase detector having a first input coupled to the output of the first delay element and a second input coupled to the output of the fourth delay element; and 
 a finite state machine having a first input coupled to an output of the first phase detector and a second input coupled to an output of the second phase detector, the finite state machine having a first output coupled to a control input of the third delay element and also to a control input of the fourth delay element, the finite state machine also having a second output coupled to a control input of the second delay element. 
 
   
   
     19. The circuit of  claim 18  wherein the first delay element comprises a fixed delay. 
   
   
     20. The circuit of  claim 18  wherein the input of the first delay element is coupled to receive a first signal and wherein the input of the second delay element is coupled to receive a second signal, wherein the first signal is a complement of the second signal. 
   
   
     21. The circuit of  claim 20  wherein the first signal is a clock signal and wherein the second signal is a clock signal. 
   
   
     22. The circuit of  claim 18  wherein the first delay element comprises a fixed delay element and wherein the second, third and fourth delay elements comprise variable delay elements such that a delay of each variable delay element can be increased or decreased based upon a signal applied to the control input of the variable delay element. 
   
   
     23. The circuit of  claim 22  wherein the finite state machine functions according to the following table: 
     
       
         
               
               
               
               
               
             
                   
                   
               
                   
                 K1 
                 K2 
                 F1 
                 F2 
               
                   
                   
               
                   
                 0 
                 0 
                 + 
                 0 
               
                   
                 0 
                 1 
                 0 
                 − 
               
                   
                 1 
                 0 
                 0 
                 + 
               
                   
                 1 
                 1 
                 − 
                 0 
               
                   
                   
               
           
              
              
              
             
             
              
              
              
              
              
             
          
         
       
       wherein K 1  comprises a signal carried at the output of the first phase detector, K 2  comprises a signal carried at the output of the second phase detector, F 1  comprises a signal carried at the first output of the finite state machine that controls an amount of delay of the third and fourth delay elements, and wherein F 2  comprises a signal carried at the second output of the finite state machine that controls an amount of delay of the second delay element. 
     
   
   
     24. The circuit of  claim 23  wherein:
 K 1  is a “0” when a signal carried at the output of the second delay element has a lesser value than a signal carried at the output of the third delay element; 
 K 1  is a “1” when the signal carried at the output of the second delay element has a greater value than the signal carried at the output of the third delay element; 
 K 2  is a “0” when a signal carried at the output of the first delay element has a lesser value than a signal carried at the output of the fourth delay element; 
 K 2  is a “1” when the signal carried at the output of the first delay element has a greater value than the signal carried at the output of the fourth delay element; 
 “+” indicates an instruction to increase a delay; and 
 “−” indicates an instruction to decrease a delay. 
 
   
   
     25. A double data rate synchronous dynamic random access memory device comprising:
 an array of memory cells arranged in rows and columns, each memory cell including a pass transistor coupled in series with a storage capacitor; 
 a row decoder coupled to the array; 
 a column decoder coupled to the array; 
 a clock receiver coupled to receive an external differential clock signal, the external differential clock signal comprising a first component carried on a first conductor and a second component carried on a second conductor; 
 a first delay element having an input coupled to the first conductor; 
 a second delay element having an input coupled to the second conductor; 
 a third delay element having an input and an output, the input of the third delay element being coupled to an output of the first delay element; 
 a fourth delay element having an input and an output, the input of the fourth delay element being coupled to an output of the second delay element; 
 a first phase detector having a first input coupled to the output of the second delay element and a second input coupled to the output of the third delay element; 
 a second phase detector having a first input coupled to the output of the first delay element and a second input coupled to the output of the fourth delay element; 
 a finite state machine having a first input coupled to an output of the first phase detector and a second input coupled to an output of the second phase detector, the finite state machine having a first output coupled to a control input of the third delay element and also to a control input of the fourth delay element, the finite state machine also having a second output coupled to a control input of the second delay element; and 
 an output buffer with a first input coupled to the output of the first delay element and a second input coupled to the output of the second delay element. 
 
   
   
     26. The device of  claim 25  wherein the first delay element comprises a fixed delay element and wherein the second, third and fourth delay elements comprise variable delay elements such that a delay of each variable delay element can be increased or decreased based upon a signal applied to the control input of the variable delay element. 
   
   
     27. The device of  claim 26  wherein the finite state machine functions according to the following table: 
     
       
         
               
               
               
               
               
             
                   
                   
               
                   
                 K1 
                 K2 
                 F1 
                 F2 
               
                   
                   
               
                   
                 0 
                 0 
                 + 
                 0 
               
                   
                 0 
                 1 
                 0 
                 − 
               
                   
                 1 
                 0 
                 0 
                 + 
               
                   
                 1 
                 1 
                 − 
                 0 
               
                   
                   
               
           
              
              
              
             
             
              
              
              
              
              
             
          
         
       
       wherein K 1  comprises a signal carried at the output of the first phase detector, K 2  comprises a signal carried at the output of the second phase detector, F 1  comprises a signal carried at the first output of the finite state machine, and wherein F 2  comprises a signal carried at the second output of the finite state machine; 
       wherein K 1  is a “0” when a signal carried at the output of the second delay element has a lesser value than a signal carried at the output of the third delay element; 
       wherein K 1  is a “1” when the signal carried at the output of the second delay element has a greater value than the signal carried at the output of the third delay element; 
       wherein K 2  is a “0” when a signal carried at the output of the first delay element has a lesser value than a signal carried at the output of the fourth delay element; 
       wherein K 2  is a “1” when the signal carried at the output of the first delay element has a greater value than the signal carried at the output of the fourth delay element; 
       wherein “+” indicates an instruction to increase a delay; and 
       wherein “−” indicates an instruction to decrease a delay. 
     
   
   
     28. The device of  claim 25  wherein the array of memory cells comprises at least one billion memory cells.