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US7250329B2ExpiredUtilityPatentIndex 63

Method of fabricating a built-in chip type substrate

Assignee: SHINKO ELECTRIC IND COPriority: May 31, 2004Filed: May 31, 2005Granted: Jul 31, 2007
Est. expiryMay 31, 2024(expired)· nominal 20-yr term from priority
Inventors:YAMANO TAKAHARUARAI TADASHI
H10W 72/9413H10W 72/874H10W 72/241H10W 72/0198H10W 70/614H10W 70/60H10W 70/09H10W 70/05H05K 3/0082H05K 1/185H05K 1/0269H05K 2201/09918H05K 3/0008H05K 3/108H05K 2201/09781H05K 3/4647H05K 1/18H05K 1/02H05K 3/30
63
PatentIndex Score
5
Cited by
11
References
5
Claims

Abstract

A method of fabricating a built-in chip type substrate containing a semiconductor chip is disclosed. The method comprises a first step of mounting the semiconductor chip on a substrate; a second step of forming chip connection wiring connected to the semiconductor chip mounted on the substrate; and a step of forming an alignment post on the substrate before the first step, the alignment post being used for positioning the chip connection wiring.

Claims

exact text as granted — not AI-modified
1. A method of fabricating a built-in chip type substrate containing a semiconductor chip comprising:
 forming an alignment post on a substrate having substantially planar surface without holes therethrough; 
 mounting the semiconductor chip on a predetermined surface of the substrate; and 
 forming a chip connection wiring connected to the semiconductor chip mounted on the substrate surface, wherein the alignment post is used for positioning the chip connection wiring,
 wherein the built-in chip type substrate is comprised of the semiconductor chip mounted on the substrate. 
 
 
     
     
       2. The method of fabricating a built-in chip type substrate as claimed in  claim 1 , wherein the alignment post is used for positioning stepper exposure of resist that patterns the chip connection wiring. 
     
     
       3. The method of fabricating a built-in chip type substrate as claimed in  claim 1 , wherein the chip connection wiring is formed on an insulation layer formed on the semiconductor chip. 
     
     
       4. The method of fabricating a built-in chip type substrate as claimed in  claim 1 , wherein the alignment post is used for positioning the semiconductor chip to be mounted on the substrate. 
     
     
       5. The method of fabricating a built-in chip type substrate as claimed in  claim 1 , wherein the alignment post is formed by Cu plating.

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