High performance vertical PNP transistor method

Abstract

The invention includes a method and resulting structure for fabricating high performance vertical NPN and PNP transistors for use in BiCMOS devices. The resulting high performance vertical PNP transistor includes an emitter region including silicon and germanium, and has its PNP emitter sharing a single layer of silicon with the NPN transistor's base. The method adds two additional masking steps to conventional fabrication processes for CMOS and bipolar devices, thus representing minor additions to the entire process flow. The resulting structure significantly enhances PNP device performance.

1. A method of forming a PNP transistor while forming a CMOS device and an NPN transistor using at least two masking steps in addition to masking steps utilized in forming the CMOS and NPN devices, the method comprising:
 a first masking step that defines a first opening through which implants for an intrinsic base and a collector of the PNP transistor are made; 
 a second masking step that defines a second opening for generating an emitter of the PNP transistor; 
 depositing a layer of polysilicon over the second opening; and 
 growing an epitaxial layer of silicon and germanium, wherein the silicon grows as a polysilicon over the polysilicon layer and as a mono-crystal silicon over the NPN. 
 
   
   
     2. The method of  claim 1 , further comprising the step of implanting an n-type isolation through the first opening to separate the PNP collector from a substrate. 
   
   
     3. The method of  claim 1 , further comprising a third masking step that defines at least one opening through which an implant for an extrinsic base of the PNP is made. 
   
   
     4. The method of  claim 1 , further comprising the step of simultaneously forming the emitter of the PNP and an extrinsic base of the NPN by implanting p-type material. 
   
   
     5. The method of  claim 4 , wherein the emitter of the PNP includes silicon and germanium. 
   
   
     6. The method of  claim 1 , wherein the epitaxial layer also includes carbon. 
   
   
     7. The method of  claim 1 , further comprising the step of adding p-type material during the growing step. 
   
   
     8. The method of  claim 1 , wherein the polysilicon layer is no less than 10 nm, and wherein the polysilicon layer is no more than 100 nm.