US7268418B2ExpiredUtilityPatentIndex 92

Multi-chips stacked package

Assignee: ADVANCED SEMICONDUCTOR ENGPriority: Apr 23, 2003Filed: Dec 30, 2003Granted: Sep 11, 2007

Est. expiryApr 23, 2023(expired)· nominal 20-yr term from priority

H10W 90/754H10W 90/734H10W 90/732H10W 74/00H10W 72/07352H10W 72/07337H10W 72/07327H10W 72/5363H10W 72/951H10W 72/884H10W 72/551H10W 72/536H10W 72/354H10W 72/321H10W 72/075H10W 72/073H10W 74/117H10W 72/30H10W 90/00H10W 72/381

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Claims

Abstract

A multi-chips stacked package at least comprises a substrate, a lower chip, an upper chip, an adhesive layer, a supporting body and an encapsulation. The lower chip is disposed on the substrate and the upper chip is attached to the lower chip via the adhesive layer. In addition, the lower chip and the upper chip are electrically connected to the substrate via first electrically conductive wires and second electrically conductive wires respectively. Furthermore, the supporting body is disposed on the lower chip and at the periphery of the upper surface of the lower chip, and covered by the upper chip. The top of the supporting body is apart from the back surface of the upper chip with a distance. Accordingly, when the second electrically conductive wires are bonded the upper chip to the substrate with a larger bonding force to cause the upper chip to be tilted more, the supporting body will support the upper chip and prevent the upper chip from contacting the first electrically conductive wires.

Claims

exact text as granted — not AI-modified

1. A multi-chips stacked package, comprising:
 a substrate having an upper surface; 
 a lower chip having a first active surface and a first back surface, wherein the lower chip is disposed above the upper surface of the substrate and electrically connected to the substrate via a plurality of first electrically conductive wires; 
 an interposer disposed on the first active surface of the lower chip; 
 an upper chip having a second active surface and a second back surface, wherein the upper chip is disposed above the interposer and electrically connected to the substrate via a plurality of second electrically conductive wires; and 
 a supporting body disposed on the upper surface of the substrate and covered by the upper chip, 
 wherein the top of the supporting body is higher than the top of the arc of each of the first electrically conductive wires and lower than the second back surface of the upper chip, and the second back surface of the upper chip is attached to the interposer, and 
 wherein an encapsulation is disposed between one of the top of the supporting body and the second back surface of the upper chip. 
 
     
     
       2. The multi-chips stacked package of  claim 1 , wherein the substrate has a first wire-bonding pad formed on the upper surface and the first wire-bonding pad is connected to the first electrically conductive wire. 
     
     
       3. The multi-chips stacked package of  claim 2 , wherein the supporting body is located between the first wire-bonding pad and a second wire-bonding pad formed on the upper surface and connected to the second electrically conductive wire. 
     
     
       4. The multi-chips stacked package of  claim 1 , wherein the supporting body surrounds the lower chip. 
     
     
       5. The multi-chips stacked package of  claim 1 , wherein the supporting body is made of epoxy. 
     
     
       6. The multi-chips stacked package of  claim 1 , wherein the supporting body is a metal bump. 
     
     
       7. The multi-chips stacked package of  claim 1 , wherein the upper chip is larger than the lower chip in size. 
     
     
       8. The multi-chips stacked package of  claim 1 , further comprising a first adhesive layer interposed between the lower chip and the interposer. 
     
     
       9. A multi-chips stacked package, comprising:
 a substrate having an upper surface; 
 a lower chip having a first active surface and a first back surface, wherein the lower chip is disposed on the upper surface of the substrate and electrically connected to the substrate via a plurality of first electrically conductive wires; 
 an interposer disposed above the first active surface of the lower chip; 
 an upper chip having a second active surface and a second back surface, wherein the upper chip is disposed above the interposer and electrically connected to the substrate via a plurality of second electrically conductive wires; and 
 a supporting body disposed on the lower chip and covered by the upper chip, 
 wherein the top of the supporting body is lower than the second back surface of the upper chip, and the second back surface is attached to the interposer, and 
 wherein an encapsulation is disposed between one of the top of the supporting body and the second back surface of the upper chip. 
 
     
     
       10. The multi-chips stacked package of  claim 9 , wherein the upper chip is larger than the lower chip in size. 
     
     
       11. The multi-chips stacked package of  claim 9 , wherein the supporting body is located at the periphery of the lower chip. 
     
     
       12. The multi-chips stacked package of  claim 9 , wherein the supporting body surrounds the interposer. 
     
     
       13. The multi-chips stacked package of  claim 9 , wherein the supporting body is made of epoxy. 
     
     
       14. The multi-chips stacked package of  claim 9 , wherein the supporting body is a metal bump. 
     
     
       15. The multi-chips stacked package of  claim 9 , wherein the interposer is a dummy chip. 
     
     
       16. The multi-chips stacked package of  claim 9 , wherein a first adhesive layer is disposed between the lower chip and the interposer. 
     
     
       17. The multi-chips stacked package of  claim 9 , wherein a second adhesive layer is disposed between the upper chip and the interposer. 
     
     
       18. The multi-chips stacked package of  claim 9 , wherein the interposer is an adhesive layer. 
     
     
       19. The multi-chips stacked package of  claim 9 , wherein the lower chip has a bonding pad formed on the first active surface of the lower chip , and connected to the first wire, and the supporting body is located between the interposer and the bonding pad. 
     
     
       20. A multi-chips stacked package, comprising:
 a substrate having an upper surface; 
 a lower chip having a first active surface and a first back surface, wherein the lower chip is disposed on the upper surface of the substrate and electrically connected to the substrate via a plurality of first electrically conductive wires; 
 an interposer disposed on the first active surface of the lower chip; 
 an upper chip having a second active surface and a second back surface, wherein the upper chip is disposed above the interposer and electrically connected to the substrate via a plurality of second electrically conductive wires; and 
 a supporting body disposed on the upper surface of the substrate and covered by the upper chip, wherein the top of the supporting body is higher than the top of the are of each of the first electrically conductive wires and lower than the second back surface of the upper chips and the second back surface is attached to the interposer, and 
 wherein an encapsulation is disposed between one of the top of the supporting body and the second back surface of the upper chip. 
 
     
     
       21. A multi-chips stacked package, comprising:
 a substrate having an upper surface; 
 a lower chip having a first active surface, a first back surface, and a bonding pad, wherein the lower chip is disposed on the upper surface of the substrate and electrically connected to the substrate via a plurality of first electrically conductive wires, and the bonding pad is formed on the first active surface of the lower chip and connected to the first electrically conductive wire; 
 an interposer disposed above the first active surface of the lower chip; 
 an upper chip having a second active surface and a second back surface, wherein the upper chip is disposed above the interposer and electrically connected to the substrate via a plurality of second electrically conductive wires; and 
 a supporting body disposed on the lower chip and covered by the upper chip, wherein the supporting body is located between the interposer and the bonding pad, and 
 wherein the top of the supporting body is lower than the second back surface of the upper chip, and the second back surface is attached to the interposer. 
 
     
     
       22. The multi-chips stacked package of  claim 21 , wherein the upper chip is larger than the lower chip in size. 
     
     
       23. The multi-chips stacked package of  claim 21 , wherein the supporting body is located at the periphery of the lower chip. 
     
     
       24. The multi-chips stacked package of  claim 21 , wherein the supporting body surrounds the interposer. 
     
     
       25. The multi-chips stacked package of  claim 21 , wherein the supporting body is made of epoxy. 
     
     
       26. The multi-chips stacked package of  claim 21 , wherein the supporting body is a metal bump.

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