Apparatus and methods for generating a column select line signal in semiconductor memory device

Abstract

An apparatus for generating a column select line signal in a semiconductor memory device includes a column select line signal generator configured to generate a column select line signal in response to a column select line enable signal. The column select line signal has a first pulse width when the column select line signal generator is in a first operational mode and a second pulse width when the column select line signal generator is in a second operational mode. The second pulse width is longer than the first pulse width.

1. An apparatus for generating a column select line signal in a semiconductor memory device, comprising:
 a column select line signal generator configured to generate a column select line signal in response to a column select line enable signal, the column select line signal having a first pulse width when the column select line signal generator is in a first operational mode and a second pulse width when the column select line signal generator is in a second operational mode, wherein the second pulse width is longer than the first pulse width a command buffer configured to receive an operation command and responsively generate an operation activation signal; and a column select line enabling unit configured to receive the operation activation signal and responsively generate a column select line enable signal; wherein the column select line signal generator is in the first operational mode when an operation command is applied to the command buffer within a predetermined number of clock cycles after a write command is applied to the command buffer, and the column select line generator is in the second operational mode when an operation command is not applied to the command buffer within the predetermined number of clock cycles after a write command is applied to the command buffer. 
 
   
   
     2. The apparatus of  claim 1 , wherein the operation command comprises one of a read command, a write command and/or a row precharge command. 
   
   
     3. The apparatus of  claim 1 , wherein the predetermined number of clock cycles is two clock cycles. 
   
   
     4. The apparatus of  claim 1 , wherein the column select line signal generator comprises:
 a column select line signal generating circuit configured to set the column select line signal in response to a column select line enable signal and to reset the column select line signal in response to a first period control signal and/or a second period control signal; and 
 a period control signal generating circuit configured to generate the first period control signal in response to an operation activation signal and to generate the second period control signal in response to a column select line disable signal. 
 
   
   
     5. The apparatus of  claim 1 , wherein a column select line disable signal is generated in response to a clock cycle following the clock cycle in which the write command is applied. 
   
   
     6. The apparatus of  claim 5 , wherein the column select line signal generator is in the first operational mode when a command is applied to the command buffer within two clock cycles after a write command is applied to the command buffer. 
   
   
     7. The apparatus of  claim 5 , wherein the column select line signal generator is in the second operational mode when a command is applied to the command buffer more than two clock cycles after a write command is applied to the command buffer. 
   
   
     8. An apparatus for generating a column select line signal in a semiconductor memory device, comprising:
 a column select line signal generator including (i) a column select line signal generating circuit configured to set the column select line signal in response to a column select line enable signal and to reset the column select line signal in response to the earlier of a first period control signal or a second period control signal, and (ii) a period control signal generating circuit configured to generate the first period control signal in response to an operation activation signal and to generate the second period control signal in response to a column select line disable signal. 
 
   
   
     9. The apparatus of  claim 8 , wherein the column select line disable signal comprises a delayed column select line disable signal. 
   
   
     10. The apparatus of  claim 8 , further comprising a delay cell configured to receive the column select line disable signal and responsively generate a delayed column select line disable signal. 
   
   
     11. The apparatus of  claim 8 , wherein the column select line disabling unit is configured to generate the column select line disable signal in response to a clock cycle of the clock signal following the clock cycle in which the operation command is applied to the command buffer. 
   
   
     12. The apparatus of  claim 11 , wherein the column select line disabling unit is configured to generate the column select line disable signal in a clock cycle that is at least two clock cycles after the clock cycle in which the operation activation signal is generated. 
   
   
     13. An apparatus for generating a column select line signal in a semiconductor memory device, comprising:
 a command buffer configured to receive an operation command and responsively generate a pre-command pulse; and 
 a column select line signal generator including (i) a column select line signal generating circuit configured to set the column select line signal in response to a column select line enable signal and to reset the column select line signal in response to the earlier of a first period control signal or a second period control signal, and (ii) a period control signal generating circuit configured to generate the first period control signal in response to the pre-command pulse and to generate the second period control signal in response to a column select line disable signal. 
 
   
   
     14. The apparatus of  claim 13 , further comprising a delay cell configured to generate a delayed column select line disable signal, wherein the period control signal generating circuit is configured to generate the second period control signal in response to the delayed column select line disable signal. 
   
   
     15. The apparatus of  claim 13 , wherein the column select line signal generator has a first operational mode when an operation command is applied to the command buffer within a predetermined number of clock cycles after a write command is applied to the command buffer, and the column select line generator has a second operational mode when an operation command is not applied to the command buffer within the predetermined number of clock cycles after a write command is applied to the command buffer, and wherein the column select line signal has a first pulse width when the column select line signal generator is in the first operational mode and a second pulse width when the column select line signal generator is in the second operational mode. 
   
   
     16. The apparatus of  claim 15 , wherein the second pulse width is longer than the first pulse width. 
   
   
     17. The apparatus of  claim 15 , wherein the predetermined number of clock cycles is two clock cycles. 
   
   
     18. A semiconductor memory device comprising:
 a memory cell array having a plurality of memory blocks in which unit memory cells each having an access transistor and a storage capacitor are connected at respective intersections between rows and columns in a matrix form; 
 a row selecting circuit for selecting rows of the memory cells; and 
 a column selecting circuit for selecting columns of the memory cells using a column select line signal, the column selecting circuit comprising a column select line signal generator comprising (i) a column select line signal generating circuit configured to set the column select line signal in response to a column select line enable signal and to reset the column select line signal in response to the earlier of a first period control signal or a second period control signal, and (ii) a period control signal generating circuit configured to generate the first period control signal in response to an operation activation signal and to generate the second period control signal in response to a column select line disable signal. 
 
   
   
     19. The device of  claim 18 , wherein the column select line signal generator has a first operational mode when an operation command is applied to the command buffer within a predetermined number of clock cycles after a write command is applied to the command buffer, and the column select line generator has a second operational mode when an operation command is not applied to the command buffer within the predetermined number of clock cycles after a write command is applied to the command buffer, and wherein the column select line signal has a first pulse width when the column select line signal generator is in the first operational mode and a second pulse width different from the first pulse width when the column select line signal generator is in the second operational mode. 
   
   
     20. The device of  claim 19 , wherein the second pulse width is longer than the first pulse width. 
   
   
     21. The device of  claim 19 , wherein the predetermined number of clock cycles is two clock cycles. 
   
   
     22. A circuit for generating a column select line signal in a semiconductor memory device, comprising:
 a continuity determination unit configured to determine if an operation command is applied within a predetermined time after a write command is applied; and 
 a signal generator operably connected to the continuity determination unit and configured to generate a column select line signal having a different pulse width depending on whether the operation command is input within the predetermined time after the write command. 
 
   
   
     23. A method for generating a column select line signal in a semiconductor memory device including a column selection circuit configured to select a column line connected to a memory cell for data access, the method comprising:
 generating a column select line signal in response to a column select line enable signal, the column select line signal having a first pulse width when the column selection circuit is in a first operational mode and a second pulse width when the column selection circuit is in a second operational mode, wherein the second pulse width is longer than the first pulse width. 
 
   
   
     24. The method of  claim 23 , wherein the predetermined number of clock cycles is two clock cycles.