Semiconductor device and interposer

Abstract

A semiconductor device characterized in that connection pads for wire bonding are arranged at peripheral regions of an electrode terminal formation surface of a semiconductor chip, test pads for testing the semiconductor chip are arranged in an inside region surrounded by said peripheral regions of said electrode terminal formation surface, and a plurality of rewiring patterns extend from the peripheral regions to said inside region of said electrode terminal formation surface and the individual rewiring patterns connect the individual electrode terminals and the corresponding connection pads and test pads.

1. A semiconductor device, comprising:
 wire bonding connection pads at peripheral regions, surrounding an inside region, of an electrode terminal formation surface of a semiconductor chip; 
 test pads to test the semiconductor chip, arranged in the inside region; and 
 a plurality of rewiring patterns, extending from respective peripheral regions to the inside region of said electrode terminal formation surface, individual ones of the plurality of rewiring patterns connecting respective, individual electrode terminals and corresponding connection pads and test pads. 
 
   
   
     2. The semiconductor device as set forth in  claim 1 , wherein
 one or more of said semiconductor devices and a semiconductor chip are carried on a wiring board, 
 connection pads of each said semiconductor device and connection electrodes of said wiring board are connected by wire bonding, and 
 each said semiconductor device and/or each said semiconductor chip is sealed by resin on said wiring board. 
 
   
   
     3. A semiconductor device as set forth in  claim 1 , wherein the electrode terminals are exposed through openings of a protective insulation layer covering said electrode terminal formation surface, the rewiring patterns extend on said protective insulation layer and are connected to said electrode terminals via said openings, said rewiring patterns and said protective insulation layer are further covered by an insulation layer, and said connection pads and said test pads, connected to said rewiring patterns, are exposed through openings in said insulation layer. 
   
   
     4. The semiconductor device as set forth in  claim 3 , wherein
 one or more of said semiconductor devices and a semiconductor chip are carried on a wiring board, 
 connection pads of each said semiconductor device and connection electrodes of said wiring board are connected by wire bonding, and 
 each said semiconductor device and/or each said semiconductor chip is sealed by resin on said wiring board. 
 
   
   
     5. A semiconductor device as set forth in  claim 1 , wherein:
 the test pads are arranged in an array on the inside region. 
 
   
   
     6. A semiconductor device as set forth in  claim 5 , characterized in that said electrode terminals are exposed through openings in a protective insulation layer covering said electrode terminal formation surface, said rewiring patterns extend on said protective insulation layer and are connected to said electrode terminals via said openings, said rewiring patterns and said protective insulation layer are further covered by an insulation layer, and said connection pads and said test pads connected to said rewiring patterns are exposed through openings in said insulation layer. 
   
   
     7. The semiconductor device as set forth in  claim 5 , wherein
 one or more of said semiconductor devices and a semiconductor chip are carried on a wiring board, 
 connection pads of each said semiconductor device and connection electrodes of said wiring board are connected by wire bonding, and 
 each said semiconductor device and/or each said semiconductor chip is sealed by resin on said wiring board.