Fabricating method of a high voltage metal oxide semiconductor device

Abstract

A high voltage metal oxide semiconductor device comprising a substrate, an N-type epitaxial layer, an isolation structure, a gate dielectric layer, a gate, an N-type drain region, a P-type well, an N-type source region, a first N-type well and a buried N-doped region is provided. The first N-type well is disposed in the N-type epitaxial layer under the isolation structure and on one side of the gate. The first N-type well overlaps with the N-type drain region. The buried N-doped region is disposed in the substrate under the N-type epitaxial layer and connected to the first N-type well.

1. A method of fabricating a high voltage metal oxide semiconductor (MOS) device, comprising the steps of:
 providing a substrate; 
 forming a buried N-doped region in the substrate; 
 forming an N-type epitaxial layer on the substrate; 
 forming a first N-type well in the N-type epitaxial layer, wherein the first N-type well and the buried N-doped region are connected; 
 forming an isolation structure in the first N-type well; 
 forming a gate dielectric layer on the N-type epitaxial layer; 
 forming a gate on the gate dielectric layer and a portion of the isolation structure; 
 forming a P-type well under a portion of the gate and in the N-type epitaxial layer on that side of the gate away from the isolation structure; and 
 forming an N-type drain region in the N-type epitaxial layer on that side of the gate close to the isolation structure and forming an N-type source region in the P-type well. 
 
   
   
     2. The method of  claim 1 , further includes forming an N-type drift region in the N-type epitaxial layer under the isolation structure. 
   
   
     3. The method of  claim 2 , wherein the N-type drift region has a dopant concentration greater than the first N-type well. 
   
   
     4. The method of  claim 2 , further includes forming a second N-type well in the N-type epitaxial layer on that side of the gate close to the isolation structure such that the second N-type well is connected to the buried N-doped region, and the second N-type well and the N-type drain region have some overlapping area. 
   
   
     5. The method of  claim 4 , wherein the second N-type well has a dopant concentration greater than the N-type drift region and the N-type drift region has a dopant concentration greater than the first N-type well. 
   
   
     6. The method of  claim 1 , further includes forming a second N-type well in the N-type epitaxial layer on that side of the gate close to the isolation structure such that the second N-type well and the buried N-doped region are connected, and the second N-type well and the N-type drain region have some overlapping area. 
   
   
     7. The method of  claim 6 , wherein the second N-type well has a dopant concentration greater than the first N-type well. 
   
   
     8. The method of  claim 1 , wherein the P-type well is formed before or after the gate. 
   
   
     9. The method of  claim 1 , wherein the isolation structure includes a field oxide layer. 
   
   
     10. The method of  claim 1 , wherein the step of forming the field oxide layer includes performing a thermal oxidation process.