Method of manufacturing nonvolatile semiconductor memory device having adjacent selection transistors connected together

Abstract

A method of manufacturing a nonvolatile semiconductor memory device, including forming a gate insulating film, a first conductive layer providing floating gates and a mask, in that order, on a semiconductor substrate, forming a plurality of element-isolating regions in the mask layer, first conductive layer, gate insulating film and semiconductor substrate; forming first trenches in parts of the first conductive layer separated by the element-isolating region; forming inter-gate insulating films on sides of each floating gate; forming control gates in the first trenches; making second trenches in parts of the mask layer and first conductive layer and in adjacent parts of the element-isolating regions; forming conductive members in the second trenches, wherein a top of the conductive members is at the same level as an upper surface of the mask layer; and removing parts of the first conductive layer and the gate insulating film exclusive of the conductive members.

1. A method of manufacturing a nonvolatile semiconductor memory device, comprising:
 forming a gate insulating film on a semiconductor substrate; 
 forming a first conductive layer on the gate insulating film; 
 forming a mask on the first conductive layer; 
 forming a plurality of element-isolating regions in the mask layer, first conductive layer, gate insulating film and semiconductor substrate; 
 making a plurality of first trenches in those parts of the first conductive layer which have been separated by the element-isolating region, the first conductive layer providing a plurality of floating gates; 
 forming inter-gate insulating films on sides of each floating gate; 
 forming second conductive layers in the first trenches, thereby forming control gates; 
 making second trenches in those parts of the mask layer and first conductive layer in which selection gates should be formed, and in those parts of the element-isolating regions which are adjacent to said parts of the mask layer and first conductive layer; 
 forming conductive members in the second trenches, a top of the conductive members is same level as an upper surface of the mask layer; and 
 removing the first conductive layer and the gate insulating film, except those parts which include the conductive members. 
 
   
   
     2. The method according to  claim 1 , further comprising forming a contact on the conductive member and the mask layer, which is formed on one of the element-isolating regions. 
   
   
     3. The method according to  claim 1 , wherein impurity ions are implanted into those parts of the semiconductor substrate which lie below the sides of each of the floating gates, thus forming source-drain regions, after the inter-gate insulating films are formed on the sides of the floating gate. 
   
   
     4. The method according to  claim 1 , wherein impurity ions are implanted into those parts of the semiconductor substrate which lie below the sides of each of the floating gates, thus forming source-drain regions, after the first trenches are made in the first conductive layer. 
   
   
     5. The method according to  claim 1 , wherein the selection gates are formed by forming a mask pattern which corresponds to the regions in which the selection gates including the conductive members, and by removing the mask layer, first conductive layer and gate insulating film. 
   
   
     6. The method according to  claim 5 , wherein the conductive members are made of material selecting from the group consisting of polysilicon and silicide. 
   
   
     7. The method according to  claim 1 , wherein the second trenches are narrower than the selection gates. 
   
   
     8. The method according to  claim 1 , wherein impurity ions are implanted into the semiconductor substrate by using the selection gates as mask, thereby forming source-drain regions, after the selection gates are formed. 
   
   
     9. The method according to  claim 1 , wherein any adjacent source-drain regions of the floating gates are connected and constitute a NAND-type semiconductor memory device. 
   
   
     10. The method according to  claim 1 , wherein any element-isolating region that is adjacent to one control gate has an upper surface lying below the upper surfaces of any other element-isolation region that is adjacent to one floating gate, and the control gates are connected to one another in the element-isolating regions, forming a word line. 
   
   
     11. The method according to  claim 1 , the forming a plurality of element-isolating regions comprising:
 forming a plurality of trenches in the mask layer, first conductive layer, gate insulating film and semiconductor substrate; 
 forming an insulating layer on the semiconductor substrate; and 
 removing the insulating layer on a surface of the mask layer by a chemical mechanical etching(CMP) using the mask layer as a stopper. 
 
   
   
     12. The method according to  claim 1 , wherein the forming inter-gate insulating films comprises depositing an insulating film in the first trenches. 
   
   
     13. The method according to  claim 1 , the forming inter-gate insulating films comprising:
 covering the floating gates by the inter-gate insulating films; and 
 removing the inter-gate insulating films on the floating gates by a chemical mechanical etching(CMP) using the mask layer as a stopper.