Methods of forming a recessed gate

Abstract

A method of forming a recessed gate may include forming a gate recess including an upper recess and a lower recess at an upper portion of a semiconductor substrate, the lower recess may have a width substantially wider than that of the upper recess, forming a gate insulation layer on an inner surface of the gate recess, forming a first silicon layer on the semiconductor substrate including the gate insulation layer to form an open void within the gate recess, forming a stop layer having a high thermal resistance on the first silicon layer to prevent a void from moving around within the gate recess, forming a second silicon layer on the first silicon layer, and patterning the second and the first silicon layers to form a gate electrode.

1. A method of forming a recessed gate, comprising:
 forming a gate recess including an upper recess and a lower recess at an upper portion of a semiconductor substrate, the lower recess having a width substantially wider than that of the upper recess; 
 forming a gate insulation layer on an inner surface of the gate recess; 
 forming a first silicon layer on the semiconductor substrate including the gate insulation layer; 
 forming a silicon oxide layer on the first silicon layer; 
 performing heat treatment on the semiconductor substrate under a reducing atmosphere to selectively remove an oxygen component from the silicon oxide layer and to form a recess-filling layer of silicon on the semiconductor substrate; 
 forming a second silicon layer on the recess-filling layer; and 
 forming a gate electrode by patterning the second silicon layer and the recess-filling layer. 
 
   
   
     2. The method as claimed in  claim 1 , wherein an upper portion of the semiconductor substrate is anisotropically etched to form the upper recess, and wherein a portion of the semiconductor substrate exposed by a bottom surface of the upper recess is isotropically etched to form the lower recess. 
   
   
     3. The method as claimed in  claim 1 , wherein forming the silicon oxide layer is performed by supplying oxygen gas or water vapor onto the first silicon layer. 
   
   
     4. The method as claimed in  claim 1 , wherein the reducing atmosphere includes hydrogen gas. 
   
   
     5. The method as claimed in  claim 4 , wherein the heat treatment is performed to remove substantially all the oxygen components from the silicon oxide layer. 
   
   
     6. The method as claimed in  claim 1 , wherein the first silicon layer is formed using amorphous silicon doped with impurities having a first concentration, and the second silicon layer is formed using polysilicon doped with impurities having a second concentration substantially lower than the first concentration. 
   
   
     7. The method as claimed in  claim 6 , wherein the first concentration is about 2.0×10 20  atoms/cm 3  to about 5.0×10 20  atoms/cm 3 , and the second concentration is about 1.0×10 20  atoms/cm 3  to about 2.0×10 20  atoms/cm 3 . 
   
   
     8. The method as claimed in  claim 1 , wherein silicon atoms included in at least one of the first silicon layer and the silicon oxide layer move toward the gate recess to form the recess-filling layer that fills up the gate recess. 
   
   
     9. The method as claimed in  claim 1 , wherein forming the first silicon layer comprises continuously forming the first silicon layer on the semiconductor substrate including the gate insulation layer. 
   
   
     10. The method as claimed in  claim 1 , wherein a ratio between the width of the upper recess and a thickness of the first silicon layer is about 1:0.3 to about 1:0.4. 
   
   
     11. The method as claimed in  claim 1 , wherein the heat treatment is performed at a temperature of about 850° C. to about 1,000° C. 
   
   
     12. A method of forming a recessed gate, comprising:
 forming a gate recess including an upper recess and a lower recess at an upper portion of a semiconductor substrate, the lower recess having a width substantially wider than that of the upper recess; 
 forming a gate insulation layer on an inner surface of the gate recess; 
 forming a first silicon layer on the semiconductor substrate including the gate insulation layer to form an open void within the gate recess; 
 forming a stop layer having a high thermal resistance on the first silicon layer to prevent a void from moving around within the gate recess; 
 forming a second silicon layer on the first silicon layer; and 
 patterning the second and the first silicon layers to form a gate electrode. 
 
   
   
     13. The method as claimed in  claim 12 , wherein the stop layer is formed using silicon oxide. 
   
   
     14. The method as claimed in  claim 13 , wherein the stop layer is formed by a thermal oxidation process. 
   
   
     15. The method as claimed in  claim 12 , prior to forming the second silicon layer, further comprising removing a portion of the stop layer that remains outside of the gate recess. 
   
   
     16. The method as claimed in  claim 15 , wherein removing the portion of the stop layer comprises removing the portion of the stop layer by at least one of a chemical mechanical polishing process and an etch-back process. 
   
   
     17. The method as claimed in  claim 12 , wherein forming the stop layer comprises forming the stop layer to have a thickness larger than a thickness of the first silicon layer. 
   
   
     18. The method as claimed in  claim 12 , wherein forming the first silicon layer comprises continuously forming the first silicon layer on the semiconductor substrate including the gate insulation layer. 
   
   
     19. The method as claimed in  claim 12 , wherein a ratio between the width of the upper recess and a thickness of the first silicon layer is about 1:0.3 to about 1:0.4. 
   
   
     20. The method as claimed in  claim 12 , wherein forming the stop layer comprises filling the open void within the gate recess with the stop layer.