Method for testing semiconductor chips using register sets

Abstract

A method for testing semiconductor chips having a test logic unit includes: providing a chip having n different register sets, each of which has m different registers that are subdivided into m register groups each having n registers, each register group respectively having only one individual register from a register set, the m register groups being uniquely identifiable using m headers; programming the m different register groups by filling them with m first bit strings, each bit string being respectively assignable to a state of n test modes; transmitting at least one header to select a register group and the state of the n test modes and executing the state of n test modes stored in the selected register group; and using a serial second bit string to read out test results or the status of the test modes.

1. A method for testing semiconductor chips, in which at least one test mode is set in a chip which is to be tested and has a test logic unit, the test mode is executed in the chip, and a status of the test mode or test results are output from the chip, the method comprising:
 providing the chip having n different register sets, each of which has m different registers that are subdivided into m register groups each having n registers, each register group respectively having only one individual register from a register set, the m register groups being uniquely identifiable using m headers, n and m being natural numbers greater than or equal to 1; 
 programming the m different register groups by filling the m different register groups with m first bit strings, each bit string being respectively assignable to a state of n test modes; 
 transmitting at least one header to select a register group and the state of the n test modes and executing the state of n test modes stored in the selected register group; and 
 using a serial second bit string to read out the test results or the status of the n test modes, 
 wherein at least one of the m first bit strings is provided with at least one binary check bit, a check bit in a first logic state being used to control the test logic unit such that those bits in a bit string that follows the check bit are skipped until another check bit in a second logic state is detected by the test logic unit, and a check bit in the second logic state being used to control the test logic unit such that those bits in a bit string that follows the check bit are not skipped until another check bit in the first logic state is detected by the test logic unit. 
 
     
     
       2. The method of  claim 1 , wherein the m first bit strings are different in the state of at least one test mode. 
     
     
       3. The method of  claim 1 , wherein the m register groups are put into a definable initial state by being filled with the m first bit strings. 
     
     
       4. The method of  claim 1 , wherein a check bit is placed in front of a bit sequence in the bit string that is associated with at least one test mode. 
     
     
       5. The method of  claim 1 , wherein a check bit is placed in front of a bit sequence in the bit string that is associated with an individual test mode. 
     
     
       6. The method of  claim 1 , wherein a check bit is placed in front of a bit sequence in the bit string that is associated with at least one test mode function. 
     
     
       7. The method of  claim 1 , wherein a check bit is placed in front of a bit sequence in the bit string that is associated with an individual test mode function. 
     
     
       8. The method of  claim 1 , wherein a check bit is placed in front of at least one bit string. 
     
     
       9. The method of  claim 1 , wherein a check bit is placed in front of all of the bit sequences that are associated with at least one test mode. 
     
     
       10. The method of  claim 1 , wherein a check bit is placed in front of all of the bit sequences that are associated with an individual test mode. 
     
     
       11. The method of  claim 1 , wherein a bit sequence that is associated with a test mode is used to activate and deactivate the test mode. 
     
     
       12. The method of  claim 1 , wherein a bit sequence that is associated with a test mode or test mode function is used to set parameters of the test mode. 
     
     
       13. A method for testing semiconductor chips, in which at least one test mode is set in a chip which is to be tested and has a test logic unit, the test mode is executed in the chip, and a status of the test mode or test results are output from the chip, the method comprising:
 providing the chip having n different register sets, each of which has m different registers that are subdivided into m register groups each having n registers, each register group respectively having only one individual register from a register set, the m register groups being uniquely identifiable using m headers, n and m being natural numbers greater than or equal to 1; 
 programming the m different register groups by filling the m different register groups with m first bit strings, each bit string being respectively assignable to a state of n test modes; 
 transmitting at least one header to select a register group and the state of the n test modes and executing the state of n test modes stored in the selected register group; and 
 using a second bit string to read out the test results or the status of the n test modes; 
 wherein the second bit string is provided with at least one binary check bit, a check bit in a first logic state being used to control the test logic unit such that those bits in a bit string that follows the check bit are skipped until another check bit in a second logic state is detected by the test logic unit, and a check bit in the second logic state being used to control the test logic unit such that those bits in the bit string that follows the check bit are not skipped until another check bit in the first logic state is detected by the test logic unit. 
 
     
     
       14. The method of  claim 13 , wherein a check bit is placed in front of a bit sequence in the bit string that is associated with at least one test mode or test mode function. 
     
     
       15. The method of  claim 13 , wherein a check bit is placed in front of a bit sequence in the bit string that is associated with an individual test mode or individual test mode function. 
     
     
       16. The method of  claim 13 , wherein a check bit is placed in front of at least one bit string. 
     
     
       17. The method of  claim 13 , wherein a check bit is placed in front of all of the bit sequences that are associated with at least one test mode or an individual test mode. 
     
     
       18. The method of  claim 13 , wherein a bit sequence that is associated with a test mode is used to activate and deactivate the test mode. 
     
     
       19. The method of  claim 13 , wherein a bit sequence that is associated with a test mode or test mode function is used to set parameters of the test mode.