Built-in design edit structures

Abstract

In an IC structure and method for debugging or adjusting the parameters of an IC circuitry, edit structures are formed in the IC device and are connected to desired portions of the IC circuitry buy forming vias through the passivation layer overlying the top metal layer and forming metal interconnects.

1. A method of debugging an integrated circuit (IC) circuitry formed in an IC structure having a top metal layer, comprising
 forming at least one device edit structure into the IC structure during fabrication of the IC structure, wherein the device edit structure is isolated from the IC circuitry by at least one isolation layer, 
 forming a passivation layer over the top metal layer, and 
 connecting the device edit structure to the IC circuitry by means of vias extending through the passivation layer and by means of laterally extending metal interconnects extending from the vias along the passivation layer. 
 
     
     
       2. A method of  claim 1 , wherein the device edit structure has a predefined value. 
     
     
       3. A method of  claim 2 , wherein the device edit structure has a predefined size and pre-defined placement. 
     
     
       4. A method of  claim 1 , wherein the device edit structure is accessed by forming vias through the passivation layer to top metal layer connections of the edit structure. 
     
     
       5. A method of  claim 4 , wherein the vias are formed by making use of a focused ion beam (FIB). 
     
     
       6. A method of  claim 5 , wherein XeF2 is used for milling openings into the passivation layer, and W (tungsten) or Pt (platinum) is used for depositing metal. 
     
     
       7. A method of adjusting the resistive or capacitive values of one or more portions of an integrated circuit (IC) circuitry, comprising
 forming one or more edit structures as part of the fabrication of the IC circuitry, and 
 connecting one or more of the edit structures to desired areas of the IC circuitry by means of vertically extending vias and horizontally extending metal interconnects. 
 
     
     
       8. A method of  claim 7 , wherein the connecting is done by forming vias through a passivation layer overlaying a top metal layer of the IC circuitry, and providing metal interconnects on the passivation layer extending to above the desired areas of the IC circuitry. 
     
     
       9. A method of  claim 8 , wherein the vias and metal interconnects are formed using focused ion beams (FIBs). 
     
     
       10. A method of  claim 9 , wherein the forming of the vias includes milling openings in the passivation layer using a FIB and then filling the opening with metal using a FIB. 
     
     
       11. A method of  claim 10 , wherein the milling is done using XeF2, and the filling is done using a tungsten (W) or platinum (Pt) FIB.