Reduction of short-circuiting between contacts at or near a tensile-compressive boundary

Abstract

Methods and apparatus are described that reduce the possibility that unintended subway short-circuits will occur between contacts of different potentials along the boundary between tensile and compressive liners (the T-C boundary). This may be done without unduly increasing the size of the semiconductor device, or even increasing the size at all over previous designs. For example, simply by adjusting the layout of the device, the contacts of two different common gates may be offset in opposing directions relative to the T-C boundary. Or, by forming a T-C boundary having a zigzag or other similar pattern, the contacts may be arranged even closer together while still reducing the likelihood of short-circuiting subways forming. Such layout adjustments do not otherwise require any additional steps or cost.

1. A semiconductor device, comprising:
 a first PFET and a first NFET sharing a common first gate; 
 a second PFET and a second NFET sharing a common second gate; 
 a compressive stress layer disposed on the first and second PFETs; 
 a tensile stress layer disposed on the first and second NFETs and contacting the compressive stress layer at a boundary; 
 a first conductive plug electrically connected to the first gate and extending through the compressive stress layer; and 
 a second conductive plug electrically connected to the second gate and extending through the tensile stress layer, 
 wherein the first and second conductive plugs are offset in opposing directions relative to the boundary. 
 
   
   
     2. The semiconductor device of  claim 1 , wherein the first conductive plug does not contact the tensile stress layer and the second conductive plug does not contact the compressive stress layer. 
   
   
     3. The semiconductor device of  claim 1 , wherein an edge of each of the first and second conductive plugs is at the boundary and extends along the boundary. 
   
   
     4. The semiconductor device of  claim 1 , wherein the first and second conductive plugs are at different voltages from each other. 
   
   
     5. The semiconductor device of  claim 1 , wherein the compressive stress layer and the tensile stress layer overlap each other at the boundary. 
   
   
     6. The semiconductor device of  claim 1 , wherein the first conductive plug extends fully through the compressive stress layer and the second conductive plug extends fully through the tensile stress layer. 
   
   
     7. A semiconductor device, comprising:
 a silicon layer; 
 a compressive stress layer disposed on a first portion of the silicon layer; 
 a tensile stress layer disposed on a second different portion of the silicon layer and contacting the compressive stress layer at a boundary, wherein the boundary has first and second portions offset from each other and a third portion connecting the first and second portions; 
 a first conductive plug extending through the compressive stress layer and disposed on a first side of the third portion of the boundary; and 
 a second conductive plug extending through the tensile stress layer and disposed on a second opposing side of the third portion of the boundary. 
 
   
   
     8. The semiconductor device of  claim 7 , wherein the first conductive plug also extends through the tensile stress layer and the second conductive plug also extends through the compressive stress layer. 
   
   
     9. The semiconductor device of  claim 7 , wherein the first and second portions of the boundary are parallel with each other and the third portion of the boundary is orthogonal to the first and second portions of the boundary. 
   
   
     10. The semiconductor device of  claim 7 , wherein an edge of the first conductive plug is at the first portion of the boundary and extends along the first portion of the boundary, and wherein an edge of the second conductive plug is at the second portion of the boundary and extends along the second portion of the boundary. 
   
   
     11. The semiconductor device of  claim 7 , further including:
 a first PFET and a first NFET sharing a common first gate that is electrically connected to the first conductive plug; and 
 a second PFET and a second NFET sharing a common second gate that is electrically connected to the second conductive plug, 
 wherein the compressive stress layer is disposed on the first and second PFETs and the tensile stress layer is disposed on the first and second NFETs. 
 
   
   
     12. The semiconductor device of  claim 7 , wherein the first and second conductive plugs are at different voltages from each other. 
   
   
     13. The semiconductor device of  claim 7 , wherein the compressive stress layer and the tensile stress layer overlap each other at the boundary. 
   
   
     14. The semiconductor device of  claim 7 , further including:
 a first polysilicon layer disposed between the compressive layer and the silicon layer and also between the tensile stress layer and the silicon layer and extending across the boundary, wherein the first polysilicon layer is electrically connected to the first conductive plug; and 
 a second polysilicon layer physically separate from the first polysilicon layer, disposed between the compressive layer and the silicon layer and also between the tensile stress layer and the silicon layer, and extending across the boundary, wherein the second polysilicon layer is electrically connected to the second conductive plug. 
 
   
   
     15. A semiconductor device, comprising:
 a silicon layer; 
 a compressive stress layer disposed on a first portion of the silicon layer; 
 a tensile stress layer disposed on a second portion of the silicon layer and contacting the compressive stress layer at a boundary; 
 a first polysilicon layer disposed between the compressive layer and the silicon layer and also between the tensile stress layer and the silicon layer and extending across the boundary; 
 a second polysilicon layer physically separate from the first polysilicon layer, disposed between the compressive layer and the silicon layer and also between the tensile stress layer and the silicon layer, and extending across the boundary; 
 a first conductive plug electrically connected to the first polysilicon layer and extending through the compressive stress layer; and 
 a second conductive plug electrically connected to the second polysilicon layer and extending through the tensile stress layer, 
 wherein the first and second conductive plugs are offset in opposing directions relative to the boundary. 
 
   
   
     16. The semiconductor device of  claim 15 , wherein the first conductive plug does not contact the tensile stress layer and the second conductive plug does not contact the compressive stress layer. 
   
   
     17. The semiconductor device of  claim 15 , wherein an edge of each of the first and second conductive plugs is at the boundary and extends along the boundary. 
   
   
     18. The semiconductor device of  claim 15 , wherein the first and second conductive plugs are at different voltages from each other. 
   
   
     19. The semiconductor device of  claim 15 , wherein the compressive stress layer and the tensile stress layer overlap each other at the boundary. 
   
   
     20. The semiconductor device of  claim 15 , wherein the first conductive plug extends fully through the compressive stress layer and the second conductive plug extends fully through the tensile stress layer.