Testing circuit and related method of injecting a time jitter

Abstract

A testing method includes selecting a low-pass filter by simulation, generating testing signals with the low-pass filter receiving output signals of an under-test circuit, and outputting the testing signals to an input of the under-test circuit for predetermined measurements. A testing circuit and testing method achieve the same jitter injection as conventional high-speed testing instruments, but save testing cost.

1. A testing method for injecting a time jitter into an under-test circuit comprising the following steps:
 simulating a frequency response and a time domain response in a testing circuit wherein the testing circuit is used for generating a testing signal; 
 choosing the testing circuit coupled to the under-test circuit wherein the frequency response and the time domain response of the simulation of the testing circuit approaches a design specification of the under-test circuit; 
 receiving an output signal of the under-test circuit; 
 generating the testing signal having a time jitter, wherein the testing signal is generated by processing the output signal of the under-test circuit; and 
 outputting the testing signal to an input of the under-test circuit. 
 
   
   
     2. The method of  claim 1  further comprising: biasing the testing signal for making the testing signal have a periodic jitter. 
   
   
     3. The method of  claim 2  wherein the step of biasing the testing signal for making the testing signal have a periodic jitter is accomplished by injecting a low-speed output signal of a low-speed testing instrument to the testing signal. 
   
   
     4. The method of  claim 3  wherein a frequency of the low-speed output signal of the low-speed testing instrument is lower than a frequency of the output signal of the under-test circuit. 
   
   
     5. The method of  claim 3  wherein a frequency of the low-speed output signal of the low-speed testing instrument equals the frequency of the periodic jitter of the testing signal. 
   
   
     6. The method of  claim 1 , wherein simulating the frequency response in a testing circuit is to calculate an insertion loss, a return loss, or an available bandwidth for the under-test circuit. 
   
   
     7. The method of  claim 1 , wherein simulating the time domain response in the testing circuit is to calculate the time jitter or a signal amplitude gain of the output signal. 
   
   
     8. A testing circuit for injecting time jitter into an under-test circuit comprising:
 an input for receiving an output signal of the under-test circuit from an output of the under-test circuit; 
 an output for outputting a testing signal of the testing circuit to an input of the under-test circuit; and 
 a first low-pass filter coupled between the input of the testing circuit and the output of the testing circuit for generating the testing signal by processing the output signal of the under-test circuit, wherein the testing signal has a time jitter. 
 
   
   
     9. The testing circuit of  claim 8  wherein the first low-pass filter comprises a first capacitor having a first terminal coupled to the input of the testing circuit. 
   
   
     10. The testing circuit of  claim 9  wherein the first capacitor comprises a capacitance for determining an insertion loss of the testing circuit and the time jitter and an amplitude of the output signal. 
   
   
     11. The testing circuit of  claim 8  further comprising an alternating current common-mode voltage-bias circuit coupled to the first low-pass filter, wherein the alternating current common-mode voltage-bias circuit receives a low-speed output signal of a low-speed testing instrument for making the testing signal have a periodic jitter. 
   
   
     12. The testing circuit of  claim 11  wherein the alternating current common-mode voltage-bias circuit has a voltage dividing circuit for determining an amplitude of the periodic jitter of the testing signal. 
   
   
     13. The testing circuit of  claim 12  wherein the alternating current common-mode voltage-bias circuit further comprises a second low-pass filter coupled between the voltage dividing circuit and the low-speed testing instrument. 
   
   
     14. The testing circuit of  claim 12  wherein the alternating current common-mode voltage-bias circuit comprises:
 a first resistor having a first terminal coupled between the first low-pass filter and the output of the testing circuit, and having a second terminal coupled to an output of the low-speed testing instrument; and 
 a second resistor having a first terminal coupled between the first low-pass filter and the output of the testing circuit, and having a second terminal coupled to ground. 
 
   
   
     15. The testing circuit of  claim 14  wherein the alternating current common-mode voltage-bias circuit further comprises a second capacitor having a first terminal coupled to the second terminal of the first resistor and a second terminal coupled to ground. 
   
   
     16. The testing circuit of  claim 8  further comprising:
 a third capacitor having a first terminal coupled to the first low-pass filter and a second terminal coupled to the output of the under-test circuit. 
 
   
   
     17. The testing circuit of  claim 16  wherein the third capacitor is utilized for alternately current coupling the output of the under-test circuit to the input of the testing circuit. 
   
   
     18. The testing circuit of  claim 11  wherein a frequency of the low-speed output signal of the low-speed testing instrument is lower than a frequency of the output signal of the under-test circuit. 
   
   
     19. The testing circuit of  claim 11  wherein a frequency of the low-speed output signal of the low-speed testing instrument equals a frequency of the periodic jitter of the testing signal. 
   
   
     20. The testing circuit of  claim 8  wherein the first low-pass filter has an insertion loss for determining the time jitter and an amplitude of the testing signal.