Swing limiter

Abstract

A swing limiter comprises a logic circuit including a first pull-up transistor and a first pull-down transistor connected between first and second nodes and which generate an output signal; a second pull-up transistor connected between a first power voltage and the first node; a second pull-down transistor connected between the second node and a second power voltage; a first control voltage generator connected between a high voltage which is higher than the first power voltage and a first reference voltage which is lower than the high voltage; and a second control voltage generator connected between a low voltage which is lower than the second power voltage and a second reference voltage which is higher than the low voltage.

1. A swing limiter, comprising:
 a logic circuit including at least one first pull-up transistor and at least one pull-down transistor which are serially connected between a first node and a first power voltage and receive at least one input signal to generate an output signal, respectively; 
 a second pull-up transistor connected between a second power voltage and the first node and causing a voltage of the first node to have a voltage level obtained by subtracting a voltage which is less than a threshold voltage thereof from the second power voltage in response to a control voltage; and 
 a control voltage generator connected between a high voltage which is higher than the second power voltage and a reference voltage which is lower than the high voltage and generating the substantially constant control voltage between the high voltage and the reference voltage, wherein the control voltage generator includes:
 first and second resistors and an NMOS transistor having a diode configuration which are serially connected between the high voltage and the reference voltage; 
 a comparator for comparing a voltage between the first and second resistors to the control voltage to generate a comparison signal; and 
 a PMOS transistor in which driving ability varies to generate the control voltage in response to the comparison signal, 
 wherein the NMOS transistor having a diode configuration has a threshold voltage which changes when the threshold voltage of the second pull-up transistor changes and generates the voltage of the second node between the first and second resistors as the control voltage. 
 
 
   
   
     2. The swing limiter of  claim 1 , wherein the swing limiter swings between the voltage level obtained by subtracting the voltage which is less than the threshold voltage of the second pull-up transistor from the second power voltage and the first power voltage level. 
   
   
     3. The swing limiter of  claim 2 , wherein the first pull-up transistor comprises a PMOS transistor, and the first pull-down transistor and the second pull-up transistors comprise an NMOS transistor. 
   
   
     4. The swing limiter of  claim 3 , wherein the control voltage generator further includes a third resistor arranged between the control voltage and the first power voltage. 
   
   
     5. The swing limiter of  claim 1 , wherein the control voltage generator comprises a transistor that has similar threshold voltage characteristics as those of the second pull-up transistor of the swing limiter. 
   
   
     6. A swing limiter, comprising:
 a logic circuit including at least one pull-up transistor and at least one first pull-down transistor which are serially connected between a first node and a first power voltage and receive at least one input signal to generate an output signal, respectively; 
 a second pull-down transistor connected between a second power voltage and the first node and causing a voltage of the first node to have a voltage level obtained by adding a voltage which is less than an absolute value of a threshold voltage thereof to the second power voltage in response to a control voltage; and 
 a control voltage generator connected between a low voltage which is lower than the second power voltage and a reference voltage which is higher than the low voltage and generating the substantially constant control voltage between the low voltage and the reference voltage, wherein the control voltage generator includes:
 first and second resistors and a PMOS transistor having a diode configuration which are serially connected between the low voltage and the reference voltage; 
 a comparator for comparing a voltage between the first and second resistors to the control voltage to generate a comparison signal; and 
 an NMOS transistor in which driving ability varies to generate the control voltage in response to the comparison signal, 
 wherein the PMOS transistor having a diode configuration has a threshold voltage which changes when the threshold voltage of the second pull-down transistor changes and generates the voltage of the second node between the first and second resistors as the control voltage. 
 
 
   
   
     7. The swing limiter of  claim 6 , wherein the swing limiter swings between the first power voltage level and the voltage level obtained by adding the voltage which is less than the absolute value of the threshold voltage of the second pull-down transistor to the second power voltage level. 
   
   
     8. The swing limiter of  claim 7 , wherein the pull-up transistor and the second pull-down transistor comprise a PMOS transistor, and the first pull-down transistor comprises an NMOS transistor. 
   
   
     9. The swing limiter of  claim 8 , wherein the control voltage generator further includes a third resistor arranged between the control voltage and the second power voltage. 
   
   
     10. The swing limiter of  claim 6 , wherein the control voltage generator comprises a transistor that has similar threshold voltage characteristics as those of the second pull-down transistor of the swing limiter. 
   
   
     11. A swing limiter, comprising:
 a logic circuit including at least one first pull-up transistor and at least one first pull-down transistor which are serially connected between a first node and a second node and receive at least one input signal to generate an output signal, respectively; 
 a second pull-up transistor connected between a first power voltage and the first node and causing a voltage of the first node to have a voltage level obtained by subtracting a voltage which is less than a threshold voltage thereof from the first power voltage in response to a first control voltage; 
 a second pull-down transistor connected between the second node and a second power voltage and causing a voltage of the second node to have a voltage level obtained by adding a voltage which is less than an absolute value of a threshold voltage thereof to the second power voltage in response to a second control voltage; 
 a first control voltage generator connected between a high voltage which is higher than the first power voltage and a first reference voltage which is lower than the high voltage and generating the substantially constant first control voltage between the high voltage and the first reference voltage; and 
 a second control voltage generator connected between a low voltage which is lower than the second power voltage and a second reference voltage which is higher than the low voltage and generating the substantially constant second control voltage between the low voltage and the second reference voltage, wherein the first control voltage generator includes
 first and second resistors and an NMOS transistor having a diode configuration which are serially connected between the high voltage and the first reference voltage; 
 a first comparator for comparing a voltage between the first and second resistors to the first control voltage to generate a first comparison signal; and 
 
 a PMOS transistor in which driving ability varies to generate the first control voltage in response to the first comparison signal, 
 wherein the NMOS transistor having a diode configuration has a threshold voltage which changes when the threshold voltage of the second pull-up transistor changes and generates a voltage of a third node between the first and second resistors as the first control voltage. 
 
   
   
     12. The swing limiter of  claim 11 , wherein the swing limiter swings between the voltage level obtained by subtracting the voltage which is less than the threshold voltage of the second pull-up transistor from the second power voltage and the voltage level obtained by adding the voltage which is less than the absolute value of the threshold voltage of the second pull-down transistor to the second power voltage. 
   
   
     13. The swing limiter of  claim 12 , wherein the first pull-up transistor and the second pull-down transistor comprise a PMOS transistor, and the first pull-down transistor and the second pull-up transistor comprise an NMOS transistor. 
   
   
     14. The swing limiter of  claim 13 , wherein the first control voltage generator further includes a third resistor arranged between the first control voltage and the first power voltage. 
   
   
     15. The swing limiter of  claim 13 , wherein the second control voltage generator includes
 third and fourth resistors and a PMOS transistor having a diode configuration which are serially connected between the low voltage and the second reference voltage; 
 a second comparator for comparing a voltage between the third and fourth resistors to the second control voltage to generate a second comparison signal; and 
 an NMOS transistor in which driving ability varies to generate the second control voltage in response to the second comparison signal, 
 wherein the PMOS transistor having a diode configuration has a threshold voltage which changes when the threshold voltage of the second pull-down transistor changes and generates a voltage of a fourth node between the third and fourth resistors as the second control voltage. 
 
   
   
     16. The swing limiter of  claim 15 , wherein the second control voltage generator further includes a fifth resistor arranged between the second control voltage and the second power voltage. 
   
   
     17. The swing limiter of  claim 11 , wherein the first control voltage generator comprises a transistor that has similar threshold voltage characteristics as those of the second pull-up transistor of the swing limiter, and a second control voltage generator comprises a transistor that has similar threshold voltage characteristics as those of the second pull-down transistor of the swing limiter. 
   
   
     18. A swing limiter, comprising:
 a logic circuit including at least one first pull-up transistor and at least one pull-down transistor which are serially connected between a first node and a first power voltage and receive at least one input signal to generate an output signal, respectively; 
 a second pull-up transistor connected between a second power voltage and the first node and causing a voltage of the first node to have a voltage level obtained by subtracting a voltage which is less than a threshold voltage thereof from the second power voltage in response to a control voltage; and 
 a control voltage generator connected between a high voltage which is higher than the second power voltage and a reference voltage which is lower than the high voltage and generating the control voltage between the high voltage and the reference voltage, wherein the swing limiter swings between the voltage level obtained by subtracting the voltage which is less than the threshold voltage of the second pull-up transistor from the second power voltage and the first power voltage level, wherein the first pull-up transistor comprises a PMOS transistor, and the first pull-down transistor and the second pull-up transistors comprise an NMOS transistor, wherein the control voltage generator includes:
 first and second resistors and an NMOS transistor having a diode configuration which are serially connected between the high voltage and the reference voltage; 
 a comparator for comparing a voltage between the first and second resistors to the control voltage to generate a comparison signal; and 
 a PMOS transistor in which driving ability varies to generate the control voltage in response to the comparison signal, 
 wherein the NMOS transistor having a diode configuration has a threshold voltage which changes when the threshold voltage of the second pull-up transistor changes and generates the voltage of the second node between the first and second resistors as the control voltage. 
 
 
   
   
     19. The swing limiter of  claim 18 , wherein the control voltage generator further includes a third resistor arranged between the control voltage and the first power voltage. 
   
   
     20. A swing limiter, comprising:
 a logic circuit including at least one pull-up transistor and at least one first pull-down transistor which are serially connected between a first node and a first power voltage and receive at least one input signal to generate an output signal, respectively; 
 a second pull-down transistor connected between a second power voltage and the first node and causing a voltage of the first node to have a voltage level obtained by adding a voltage which is less than an absolute value of a threshold voltage thereof to the second power voltage in response to a control voltage; and 
 a control voltage generator connected between a low voltage which is lower than the second power voltage and a reference voltage which is higher than the low voltage and generating the control voltage between the low voltage and the reference voltage, wherein the swing limiter swings between the first power voltage level and the voltage level obtained by adding the voltage which is less than the absolute value of the threshold voltage of the second pull-down transistor to the second power voltage level, wherein the pull-up transistor and the second pull-down transistor comprise a PMOS transistor, and the first pull-down transistor comprises an NMOS transistor, wherein the control voltage generator includes:
 first and second resistors and a PMOS transistor having a diode configuration which are serially connected between the low voltage and the reference voltage; 
 a comparator for comparing a voltage between the first and second resistors to the control voltage to generate a comparison signal; and 
 an NMOS transistor in which driving ability varies to generate the control voltage in response to the comparison signal, 
 wherein the PMOS transistor having a diode configuration has a threshold voltage which changes when the threshold voltage of the second pull-down transistor changes and generates the voltage of the second node between the first and second resistors as the control voltage. 
 
 
   
   
     21. The swing limiter of  claim 20 , wherein the control voltage generator further includes a third resistor arranged between the control voltage and the second power voltage. 
   
   
     22. A swing limiter, comprising:
 a logic circuit including at least one first pull-up transistor and at least one first pull-down transistor which are serially connected between a first node and a second node and receive at least one input signal to generate an output signal, respectively; 
 a second pull-up transistor connected between a first power voltage and the first node and causing a voltage of the first node to have a voltage level obtained by subtracting a voltage which is less than a threshold voltage thereof from the first power voltage in response to a first control voltage; 
 a second pull-down transistor connected between the second node and a second power voltage and causing a voltage of the second node to have a voltage level obtained by adding a voltage which is less than an absolute value of a threshold voltage thereof to the second power voltage in response to a second control voltage; 
 a first control voltage generator connected between a high voltage which is higher than the first power voltage and a first reference voltage which is lower than the high voltage and generating the first control voltage between the high voltage and the first reference voltage; and 
 a second control voltage generator connected between a low voltage which is lower than the second power voltage and a second reference voltage which is higher than the low voltage and generating the second control voltage between the low voltage and the second reference voltage, wherein the swing limiter swings between the voltage level obtained by subtracting the voltage which is less than the threshold voltage of the second pull-up transistor from the second power voltage and the voltage level obtained by adding the voltage which is less than the absolute value of the threshold voltage of the second pull-down transistor to the second power voltage, wherein the first pull-up transistor and the second pull-down transistor comprise a PMOS transistor, and the first pull-down transistor and the second pull-up transistor comprise an NMOS transistor, wherein the control voltage generator includes:
 first and second resistors and an NMOS transistor having a diode configuration which are serially connected between the high voltage and the first reference voltage; 
 a first comparator for comparing a voltage between the first and second resistors to the first control voltage to generate a first comparison signal; and 
 a PMOS transistor in which driving ability varies to generate the first control voltage in response to the first comparison signal, 
 wherein the NMOS transistor having a diode configuration has a threshold voltage which changes when the threshold voltage of the second pull-up transistor changes and generates a voltage of a third node between the first and second resistors as the first control voltage. 
 
 
   
   
     23. The swing limiter of  claim 22 , wherein the first control voltage generator further includes a third resistor arranged between the first control voltage and the first power voltage. 
   
   
     24. The swing limiter of  claim 22 , wherein the second control voltage generator includes:
 third and fourth resistors and a PMOS transistor having a diode configuration which are serially connected between the low voltage and the second reference voltage; 
 a second comparator for comparing a voltage between the third and fourth resistors to the second control voltage to generate a second comparison signal; and 
 an NMOS transistor in which driving ability varies to generate the second control voltage in response to the second comparison signal, 
 wherein the PMOS transistor having a diode configuration has a threshold voltage which changes when the threshold voltage of the second pull-down transistor changes and generates a voltage of a fourth node between the third and fourth resistors as the second control voltage. 
 
   
   
     25. The swing limiter of  claim 24 , wherein the second control voltage generator further includes a fifth resistor arranged between the second control voltage and the second power voltage.