Semiconductor memory device and data write and read method thereof

Abstract

A semiconductor memory device includes a serial to parallel converter configured to generate parallel data at a parallel data rate in response to first serial data at first serial data rate in a first mode and configured to generate the parallel data at the parallel data rate in response to a second serial data at second serial data rate in a second mode, wherein the second serial data rate is less than the first serial data rate, and a data write circuit configured to provide the parallel data to a memory cell array.

1. A semiconductor memory device, comprising:
 a memory cell array for writing and reading data; 
 a clock signal generating means for receiving an external clock signal applied from an external portion to generate first and second clock signals having the same phase and frequency as the external clock signal during a normal operation including a normal read operation and a normal write operation and to generate the first clock signal having the same phase and frequency as the external clock signal and the second clock signal having the same phase as and a higher frequency than the external clock signal during a test operation including a test read operation and a test write operation; 
 a data write means for receiving a first predetermined-bit serial input data applied at a first data rate and converting the first predetermined-bit serial input data into a first predetermined-bit parallel input data in response to the first clock signal during the normal write operation and for receiving and converting a second predetermined-bit serial input data having a second predetermined-bit number that is smaller than a first predetermined-bit number of the first predetermined-bit serial input data into a second predetermined-bit parallel input data, and extending the second predetermined-bit parallel input data to the first predetermined-bit number to generate the first predetermined-bit parallel input data in response to the second clock signal during the test write operation, and for outputting the first predetermined-bit parallel input data to the memory cell array in response to the first clock signal during the normal write operation and the test write operation; and 
 a data read means for generating a first predetermined-bit parallel output data outputted from the memory cell array in response to the first clock signal during the normal read operation and the test read operations, converting the first predetermined-bit parallel output data into serial output data and outputting the serial output data at the first data rate in response to the second clock signal during the normal read operation, and converting the predetermined-bit parallel output data into serial data and outputting the serial output data at a second data rate in response to the second clock signal during the test read operation. 
 
   
   
     2. The semiconductor memory device of  claim 1 , wherein the frequency of the external clock signal applied for the test operation is lower than the frequency of the external clock signal applied for the normal operation. 
   
   
     3. The semiconductor memory device of  claim 2 , wherein the clock signal generating means includes
 a delay locked loop for detecting a phase difference between the external clock signal and the first clock signal to generate a delay clock signal; 
 a first clock signal generator for generating the delay clock signal as the first clock signal during the normal operation and for delaying the delay clock signal during a predetermined time and then generating the delayed delay clock signal as the first clock signal during the test operation; and 
 a second clock signal generator for generating the delay clock signal as the second clock signal during the normal operation and for multiplying a frequency of the delay clock signal by a predetermined number to generate the second clock signal, 
 wherein the predetermined time is identical to a time spent for the second clock signal generator to multiply the frequency of the delay clock signal by the predetermined number to generate the second clock signal. 
 
   
   
     4. The semiconductor memory device of  claim 3 , wherein the data read means includes
 a data read circuit for receiving and outputting the first predetermined-bit parallel output data outputted from the memory cell array in response to the first clock signal during the normal read operation and the test read operation; and 
 a parallel-to-serial converter for converting the first predetermined-bit parallel output data outputted from the data read circuit into the serial output data and outputting the serial output data at the first data rate in response to the second clock signal during the normal read operation and for converting the first predetermined-bit parallel output data outputted from the data read circuit into the serial output data and outputting the serial output data at a third data rate in response to the second clock signal during the test read operation. 
 
   
   
     5. The semiconductor memory device of  claim 4 , further comprising: the data write means includes
 a serial-to-parallel converter for receiving and converting the first predetermined-bit serial input data applied at the first data rate into the first predetermined-bit parallel input data in response to the first clock signal during the normal write operation and for receiving and converting the second predetermined-bit serial input data having the second predetermined-bit number which is smaller than the first predetermined-bit number applied at the first data rate into the second predetermined-bit parallel input data and extending the second predetermined-bit parallel input data to the first predetermined-bit number to generate the first predetermined-bit parallel input data, in response to the second clock signal during the test write operation; and 
 a data write circuit for receiving and writing the first predetermined-bit parallel input data outputted from the serial-to-parallel converter onto the memory cell array in response to the first clock signal during the normal write operation and the test write operation. 
 
   
   
     6. The semiconductor device of  claim 2 , wherein the first data rate is a data rate which transmits data of a predetermined times of the second data rate within one cycle of the external clock signal. 
   
   
     7. The semiconductor device of  claim 6 , wherein the first data rate is a double data rate, and the second data rate is a quad data rate. 
   
   
     8. The semiconductor memory device of  claim 7 , further comprising: a mode setting means for receiving a code signal applied from an external portion to generate a selection signal for selecting the normal operation or the test operation and a burst length signal for setting the bit number of the predetermined-bit serial input and output data inputted from and outputted to an external portion, during a mode setting operation. 
   
   
     9. The device of  claim 8 , further comprising
 an enable clock signal generator for generating a write enable clock signal in response to the second clock signal during the normal write operation and the test write operation and for generating a read enable clock signal for outputting the predetermined-bit serial data in response to the second clock signal and the burst length signal during the normal read operation and the test read operation. 
 
   
   
     10. A semiconductor memory device, comprising:
 an address input means for receiving and buffering an address which is sequentially applied at least twice in response to a rising edge of an external clock signal applied from an external portion during a normal operation including a normal read operation and a normal write operation and for receiving and buffering an address which is sequentially applied at least twice in response to rising and falling edges of the external clock signal during a test operation including a test read operation and a test write operation; 
 a memory cell array for writing and reading data in at least one cell which the address designates; 
 a clock signal generating means for receiving the external clock signal to generate first and second clock signals which have the same phase and frequency as the external clock signal during the normal operation and to generate the first clock signal which has the same phase and frequency as the external clock signal and the second clock signal which has the same phase as and a higher frequency than the external clock signal during the test operation; 
 a data write means for receiving a first predetermined-bit serial input data applied at a first data rate and converting the first predetermined-bit serial input data into a first predetermined-bit parallel input data to be outputted to the memory cell array during the normal write operation, and for receiving and converting a second predetermined-bit serial input data having a second predetermined-bit number that is smaller than a first predetermined-bit number of the first predetermined-bit serial input data into a second predetermined-bit parallel input data, extending the second predetermined-bit parallel input data to the first predetermined-bit number to generate the first predetermined-bit parallel input data, and outputting the first predetermined- bit parallel input data to the memory cell array during the test write operation; and 
 a data read means for generating a predetermined-bit parallel output data outputted from the memory cell array in response to the first clock signal during the normal and test operations, converting the predetermined-bit parallel output data into serial output data and outputting the serial output data at the first data rate in response to the second clock signal during the normal read operation, and converting the predetermined-bit parallel output data into the serial output data and outputting the serial data at a second data rate in response to the second clock signal during the test read operation. 
 
   
   
     11. The device of  claim 10 , wherein the frequency of the external clock signal applied for the normal operation is higher than the frequency of the external clock signal applied for the test operation. 
   
   
     12. The device of  claim 11 , wherein the clock signal generating means includes
 a clock buffer for buffering the external clock signal to generate a buffered clock signal; 
 a delay locked loop for detecting a phase difference between the external clock signal and the first clock signal to generate a delay clock signal; 
 a first clock signal generator for generating the delay clock signal as the first clock signal during the normal operation and for delaying the delay clock signal during a predetermined time and then generating the delayed delay clock signal as the first clock signal during the test operation; and 
 a second clock signal generator for generating the delay clock signal as the second clock signal during the normal operation and for multiplying a frequency of the delay clock signal by a predetermined number to generate the second clock signal, 
 wherein the predetermined time is identical to a time spent for the second clock signal generator to multiply the frequency of the delay clock signal by the predetermined number to generate the second clock signal. 
 
   
   
     13. The device of  claim 12 , wherein the address input means buffers an address which is serially inputted twice to generate first and second addresses in response to a rising edge of the buffered clock signal during the normal operation, buffering an address which is serially inputted twice to generate first and second addresses in response to rising and falling edges of the buffered clock signal during the test operation, and making up one address using the first and second addresses. 
   
   
     14. The device of  claim 13 , wherein the address input means includes
 a first address input buffer for buffering the address to generate the first address in response to the buffered clock signal during the normal operation and the test operation; 
 a delay for delaying the buffered address during one clock cycle to generate the second address in response to the buffered clock signal during the normal operation; and 
 a second address input buffer for buffering the address to generate the second address in response to an opposite phase signal of the buffered clock signal during the test operation. 
 
   
   
     15. The device of  claim 13 , wherein the data read means includes:
 a data read circuit for receiving and outputting the predetermined-bit parallel output data outputted from the memory cell array in response to the first clock signal during the normal read operation and the test read operation; and 
 a parallel-to-serial converter for converting the predetermined-bit parallel output data outputted from the data read circuit into the serial output data and outputting the serial output data at the first data rate in response to the second clock signal during the normal read operation and the test read operation. 
 
   
   
     16. The device of  claim 11 , wherein the data write means includes:
 a serial-to-parallel converter for receiving and converting the first predetermined-bit serial input data applied at the first data rate into the first predetermined-bit parallel input data in response to the first clock signal during the normal write operation and for receiving and converting the second predetermined-bit serial input data having the second predetermined-bit number that is smaller than the first predetermined-bit number applied at the first data rate into the second predetermined-bit parallel input data and extending the second predetermined-bit parallel input data to the first predetermined-bit number to generate the first predetermined-bit parallel input data, in response to the second clock signal during the test write operation; and 
 a data write circuit for writing the first predetermined-bit parallel input data onto the memory cell array in response to the first clock signal during the normal write operation and the test write operation. 
 
   
   
     17. The device of  claim 11 , wherein the first data rate is a double data rate, and the second data rate is a quad data rate. 
   
   
     18. The device of  claim 17 , further comprising, a mode setting means for receiving a code signal applied from an external portion to generate a selection signal for selecting the normal operation or the test operation and a burst length signal for setting the bit number of the predetermined-bit serial input and output data, during a mode setting operation. 
   
   
     19. The device of  claim 18 , further comprising, an enable clock signal generator for generating a write enable clock signal in response to the second clock signal during the normal write operation and the test write operation and for generating a read enable clock signal for outputting the predetermined-bit serial output data in response to the second clock signal and the burst length signal during the normal read operation and the test read operation. 
   
   
     20. A data write and read method of a semiconductor memory device, comprising:
 receiving an external clock signal applied from an external portion; 
 generating first and second clock signals which have the same phase and frequency as the external clock signal during a normal operation including a normal read operation and a normal write operation and generating the first clock signal which has the same phase and frequency as the external clock signal and the second clock signal which has the same phase as and a higher frequency than the external clock signal during a test operation including a test read operation and a test write operation; 
 receiving a first predetermined-bit serial input data applied at a first data rate; 
 converting the first predetermined-bit serial input data into parallel input data to be outputted to the memory cell array during the normal write operation and receiving and converting a second predetermined-bit input serial data into the parallel input data to be outputted to the memory cell array in response to the second clock signal during the test write operation; 
 reading a predetermined-bit parallel output data outputted from the memory cell array in response to the first clock signal during the normal and test operations; 
 converting the predetermined-bit parallel output data into serial output data and outputting the serial output data at the first data rate in response to the second clock signal during the normal read operation and converting the predetermined-bit parallel output data into serial output data and outputting the serial output data at a second data rate in response to the second clock signal during the test read operation. 
 
   
   
     21. The method of  claim 20 , wherein the frequency of the external clock signal applied for the test operation is lower than the frequency of the external clock signal applied for the normal operation. 
   
   
     22. The method of  claim 20 , wherein generating first and second clock signals includes:
 detecting a phase difference between the external clock signal and the first clock signal to generate a delay clock signal; 
 generating the delay clock signal as the first clock signal during the normal operation and delaying the delay clock signal during a predetermined time and then generating the delayed delay clock signal as the first clock signal during the test operation; and 
 generating the delay clock signal as the second clock signal during the normal operation and for multiplying a frequency of the delay clock signal by a predetermined number to generate the second clock signal, 
 wherein the predetermined time is identical to a time spent to multiply the frequency of the delay clock signal by the predetermined number to generate the second clock signal. 
 
   
   
     23. The method of  claim 20 , the predetermined-bit parallel output data being referred to as first predetermined-bit parallel output data, wherein converting the second predetermined-bit serial input data into the parallel input data includes:
 during the test write operation, converting the second predetermined-bit serial input data into second predetermined-bit parallel input data to generate the first predetermined-bit parallel input data if a second predetermined-bit number of the second predetermined-bit parallel input data is equal to a first predetermined-bit number of the first predetermined-bit parallel input data, and 
 converting the second predetermined-bit serial input data into parallel input data to generate the first predetermined-bit parallel input data if the second predetermined-bit number is smaller than the first predetermined-bit number during the test write operation. 
 
   
   
     24. The method of  claim 20 , wherein the first data rate is a data rate which transmits data of a predetermined times of the second data rate within one cycle of the external clock signal. 
   
   
     25. A data write and read method of a semiconductor memory device, comprising:
 receiving and buffering an address which is sequentially applied at least twice in response to a rising edge of an external clock signal applied from an external portion during a normal operation including a normal read operation and a normal write operation and for receiving and buffering an address which is sequentially applied at least twice in response to rising and falling edges of the external clock signal during a test operation including a test read operation and a test write operation; 
 receiving the external clock signal to generate first and second clock signals which have the same phase and frequency as the external clock signal during the normal operation and to generate the first clock signal which has the same phase and frequency as the external clock signal and the second clock signal which has the same phase as and a higher frequency than the external clock signal during the test operation; 
 receiving a first predetermined-bit serial input data applied at a first data rate and converting the first predetermined-bit serial input data into parallel input data to be outputted to a memory cell array during the normal write operation and receiving a second predetermined-bit serial input data applied at the first data rate and converting the second predetermined-bit serial input data into the parallel input data to be outputted to the memory cell array in response to the second clock signal during the test write operation; 
 reading a predetermined-bit parallel output data outputted from the memory cell array in response to the first clock signal during the normal and test operations; and 
 converting the predetermined-bit parallel output data into serial output data and outputting the predetermined-bit serial output data at the first data rate in response to the second clock signal during the normal read operation, and converting the predetermined-bit parallel output data into serial output data and outputting the serial output data at the a second data rate in response to the second clock signal during the test read operation. 
 
   
   
     26. The method of  claim 25 , wherein the frequency of the external clock signal applied for the normal operation is higher than the frequency of the external clock signal applied for the test operation. 
   
   
     27. The method of  claim 26 , wherein receiving a second predetermined-bit serial data includes:
 during the test write operation, converting the second predetermined-bit serial input data into the second predetermined-bit parallel input data to generate the first predetermined-bit parallel data if a second predetermined-bit number of the second predetermined-bit parallel input data is equal to a first predetermined-bit number of the first predetermined-bit parallel input data; and 
 converting the second predetermined-bit serial input data into second predetermined-bit parallel input data to generate the first predetermined-bit parallel input data if the second predetermined-bit number is smaller than the first predetermined-bit number during the test write operation. 
 
   
   
     28. The method of  claim 26 , wherein the first data rate is a data rate which transmits data of a predetermined times of the second data rate within one cycle of the external clock signal. 
   
   
     29. The method of  claim 25 , wherein receiving the external clock signal to generate first and second clock signals includes
 buffering the external clock signal to generate a buffered clock signal; 
 detecting a phase difference between the external clock signal and the first clock signal to generate a delay clock signal; 
 a first clock signal generating step for generating the delay clock signal as the first clock signal during the normal operation and for delaying the delay clock signal during a predetermined time and then generating the delayed delay clock signal as the first clock signal during the test operation; and 
 a second clock signal generating step for generating the delay clock signal as the second clock signal during the normal operation and for multiplying a frequency of the delay clock signal by a predetermined number to generate the second clock signal, 
 wherein the predetermined time is identical to a time spent to multiply the frequency of the delay clock signal by the predetermined number to generate the second clock signal at the second clock signal generating step. 
 
   
   
     30. The device of  claim 29 , wherein receiving and buffering an address includes
 buffering an address which is serially inputted twice to generate first and second addresses in response to a rising edge of the buffered clock signal during the normal operation; 
 buffering an address which is serially inputted twice to generate first and second addresses in response to rising and falling edges of the buffered clock signal during the test operation; and 
 making up one address using the first and second addresses. 
 
   
   
     31. The method of  claim 29 , wherein receiving and buffering an address includes
 buffering the address to generate the first address in response to the buffered clock signal during the normal operation and the test operation; 
 delaying the buffered address during one clock cycle to generate the second address in response to the buffered clock signal during the normal operation; and 
 buffering the address to generate the second address in response to an opposite phase signal of the buffered clock signal during the test operation.