Source side injection storage device with spacer gates and method therefor

Abstract

A storage device structure ( 10 ) has two bits of storage per control gate ( 34 ) and uses source side injection (SSI) to provide lower programming current. A control gate ( 34 ) overlies a drain electrode formed by a doped region ( 22 ) that is positioned in a semiconductor substrate ( 12 ). Two select gates ( 49 and 50 ) are implemented with conductive sidewall spacers adjacent to and lateral to the control gate ( 34 ). A source doped region ( 60 ) is positioned in the semiconductor substrate ( 12 ) adjacent to one of the select gates for providing a source of electrons to be injected into a storage layer ( 42 ) underlying the control gate. Lower programming results from the SSI method of programming and a compact memory cell size exists.

1. A method for forming a storage device structure comprising
 providing a semiconductor substrate; 
 forming a first plurality of spaced apart doped regions in the semiconductor substrate; 
 forming a plurality of spaced apart storage regions over the first plurality of spaced apart doped regions; 
 forming a plurality of spaced apart first electrodes over the plurality of spaced apart storage regions; 
 forming first sidewall spacers on sidewalls of the plurality of spaced apart first electrodes, wherein the first sidewall spacers comprise one of a group consisting of a material that can be doped to become conductive and a first conductive material; 
 implanting dopants using the first sidewall spacers as a mask to form a second plurality of spaced apart doped regions in the semiconductor substrate; 
 forming a second conductive material over the second plurality of spaced apart doped regions; and 
 forming contacts that electrically connect the second conductive material and the second plurality of spaced apart doped regions. 
 
     
     
       2. The method of  claim 1 , wherein the plurality of spaced apart first electrodes are characterized as control gates and the first sidewall spacers are characterized as select gates. 
     
     
       3. A method for forming a storage device structure comprising:
 providing a semiconductor substrate; 
 forming a first plurality of spaced apart doped regions in the semiconductor substrate; 
 forming a plurality of spaced apart storage regions over the first plurality of spaced apart doped regions; 
 forming a plurality of spaced apart first electrodes over the plurality of spaced apart storage regions; 
 forming first sidewall spacers on sidewalls of the plurality of spaced apart first electrodes, wherein the first sidewall spacers comprise one of a group consisting of a material that can be doped to become conductive and a material that is conductive; 
 implanting dopants using the first sidewall spacers as a mask to form a second plurality of spaced apart doped regions in the semiconductor substrate, wherein the forming the first plurality of spaced apart doped regions comprises: 
 forming spaced apart sacrificial layers over the semiconductor substrate, wherein the spaced apart sacrificial layers have sidewalls; 
 forming second sidewall spacers on the sidewalls of the spaced apart sacrificial layers; and 
 implanting into the semiconductor substrate using the spaced apart sacrificial layers and the second sidewall spacers as a mask. 
 
     
     
       4. The method of  claim 1 , wherein forming the first sidewall spacers comprises:
 forming a conformal layer over the plurality of spaced apart first electrodes, wherein the conformal layer comprises one of the group consisting of a material that can be doped to become conductive and a third conductive material; and 
 anisotropically etching the conformal layer to leave the first sidewall spacers on the sidewalls of the plurality of spaced apart first electrodes. 
 
     
     
       5. The method of  claim 4 , wherein the conformal layer is characterized as comprising polysilicon. 
     
     
       6. A method for forming a storage device structure comprising
 providing a semiconductor substrate; 
 forming a first plurality of spaced apart doped regions in the semiconductor substrate; 
 forming a plurality of spaced apart nitride film regions over the first plurality of spaced apart doped regions, each of which stores charge; 
 forming a plurality of spaced apart first electrodes over the plurality of spaced apart nitride film regions; 
 forming first sidewall spacers on sidewalls of the plurality of spaced apart first electrodes, wherein the first sidewall spacers comprise one of a group consisting of a material that can be doped to become conductive and a first material that is conductive; 
 implanting dopants using the first sidewall spacers as a mask to form a second plurality of spaced apart doped regions in the semiconductor substrate; 
 forming a second material that is conductive over the second plurality of spaced apart doped regions; and 
 forming contacts between the second material that is conductive and the second plurality of spaced apart doped regions. 
 
     
     
       7. The method of  claim 6 , wherein the plurality of spaced apart first electrodes are characterized as control gates and the first sidewall spacers are characterized as select gates. 
     
     
       8. The method of  claim 6  wherein the forming the first plurality of spaced apart doped regions comprises:
 forming spaced apart sacrificial layers over the semiconductor substrate, wherein the spaced apart sacrificial layers have sidewalls; 
 forming second sidewall spacers on the sidewalls of the spaced apart sacrificial layers; and 
 implanting into the semiconductor substrate using the spaced apart sacrificial layers and the second sidewall spacers as a mask. 
 
     
     
       9. The method of  claim 6 , wherein forming the first sidewall spacers comprises:
 forming a conformal layer over the plurality of spaced apart first electrodes, wherein the conformal layer comprises one of the group consisting of a material that can be doped to become conductive and a third material that is conductive; and 
 anisotropically etching the conformal layer to leave the first sidewall spacers on the sidewalls of the plurality of spaced apart first electrodes. 
 
     
     
       10. The method of  claim 9 , wherein the conformal layer is characterized as comprising polysilicon. 
     
     
       11. A method for forming a storage device structure comprising:
 providing a semiconductor substrate; 
 forming a first plurality of spaced apart doped regions in the semiconductor substrate; 
 forming a plurality of spaced apart storage regions over the first plurality of spaced apart doped regions; 
 forming a plurality of spaced apart first electrodes over the plurality of spaced apart storage regions; 
 forming first sidewall spacers on sidewalls of the plurality of spaced apart first electrodes, wherein the first sidewall spacers comprise one of a group consisting of a material that can be doped to become conductive and a first conductive material; 
 implanting dopants using the first sidewall spacers as a mask to form a second plurality of spaced apart doped regions in the semiconductor substrate; 
 forming an insulating layer overlying the plurality of spaced apart first electrodes and the first sidewall spacers; 
 forming a conductive layer overlying the insulating layer; connecting the conductive layer to the second plurality of spaced apart doped regions in the semiconductor substrate; 
 forming a second conductive material over the second plurality of spaced apart doped regions; and 
 forming contacts between the second conductive material and the second plurality of spaced apart doped regions. 
 
     
     
       12. The method of  claim 11 , wherein the plurality of spaced apart first electrodes are characterized as control gates and the first sidewall spacers are characterized as select gates. 
     
     
       13. The method of  claim 11  wherein the forming the first plurality of spaced apart doped regions comprises:
 forming spaced apart sacrificial layers over the semiconductor substrate, wherein the spaced apart sacrificial layers have sidewalls; 
 forming second sidewall spacers on the sidewalls of the spaced apart sacrificial layers; and 
 implanting into the semiconductor substrate using the spaced apart sacrificial layers and the second sidewall spacers as a mask. 
 
     
     
       14. The method of  claim 11 , wherein forming the first sidewall spacers comprises:
 forming a conformal layer over the plurality of spaced apart first electrodes, wherein the conformal layer comprises one of the group consisting of a material that can be doped to become conductive and a third conductive material; and 
 anisotropically etching the conformal layer to leave the first sidewall spacers on the sidewalls of the plurality of spaced apart first electrodes. 
 
     
     
       15. The method of  claim 14 , wherein the conformal layer is characterized as comprising polysilicon.