Method for forming a damascene pattern of a copper metallization layer

Abstract

There is provided a method of forming a damascene pattern including a via and a trench in a damascene process of forming a copper metal interconnection. The method includes forming an interlayer dielectric layer on a substrate, forming a first photosensitive layer pattern including a first opening that exposes a region in which a via is to be formed on the interlayer dielectric layer, etching the interlayer dielectric layer to a first depth using the first photosensitive layer pattern as an etching mask, removing the first photosensitive layer pattern and forming a second photosensitive layer pattern including a second opening that exposes a region in which a trench is to be formed on the interlayer dielectric layer, and etching the interlayer dielectric layer using the second photosensitive layer pattern as an etching mask to simultaneously form the via and the trench.

1. A method of forming a damascene pattern including a via and a trench in a damascene process of forming a copper metal interconnection, comprising:
 forming an interlayer dielectric layer on a substrate; 
 forming a first photosensitive layer pattern including a first opening that exposes a region in which a via is to be formed on the interlayer dielectric layer; 
 etching the interlayer dielectric layer to a first depth using the first photosensitive layer pattern as an etching mask; 
 removing the first photosensitive layer pattern and forming a second photosensitive layer pattern including a second opening that exposes a region in which a trench is to be formed on the interlayer dielectric layer; 
 forming plasma reaction by-product layers on sidewalls of the second photosensitive pattern in the second opening; and 
 etching the interlayer dielectric layer using the second photosensitive layer pattern and the plasma reaction by-product layers as an etching mask to simultaneously form the via and the trench. 
 
     
     
       2. The method according to  claim 1 , wherein the first depth is no less than 50% and no more than 80% of a thickness of the interlayer dielectric layer. 
     
     
       3. The method according to  claim 1 , wherein
 forming the interlayer dielectric layer comprises forming a barrier insulating layer between the substrate and the interlayer dielectric layer; and 
 etching the interlayer dielectric layer further comprises sequentially etching the interlayer dielectric layer and the barrier insulating layer. 
 
     
     
       4. The method according to  claim 3 , wherein the first depth is no less than 50% and no more than 80% of the total thickness of the interlayer dielectric layer and the barrier insulating layer.