Leakage current control circuit with a single low voltage power supply and method thereof

Abstract

A leakage current control circuit with a single low voltage power supply is provided. The circuit includes a first power supply line, a second power supply line, a ground line, a high voltage generating circuit, a power transistor and a control circuit. The high voltage generating circuit generates a voltage in response to an internal sleep signal. The gate electrode of the power transistor is connected to the output of the high-voltage generating circuit such that the power transistor is controlled by the high voltage generating circuit. When the power transistor turns on, the circuit is in operation mode; when the power transistor is off, the circuit is in sleep mode. The control circuit connects to the first power line, the second power line, and the ground line to output the internal sleep signal in response to the sleep signal.

1. A leakage current control circuit with a single low voltage power supply, operating in a sleep mode or an active mode in response to an internal sleep mode signal, comprising:
 a first power supply line connected to a plurality of first components, the plurality of first components including one of a plurality of flip-flops and a plurality of combinational circuits; 
 a second power supply line connected to a plurality of second components, the plurality of second components including an other of the plurality of flip-flops and the plurality of combinational circuits, each of the plurality of first components and the plurality of second components being connected to different ones of the first and second power supply lines, respectively; 
 a first ground line; 
 a high-voltage generating circuit for generating an output voltage in response to the internal sleep mode signal; 
 a power transistor having a first end, a second end and a gate electrode, wherein the first end is connected to the said first power supply line, the second end is connected to the second power supply line, the gate electrode is connected to the output of the said high-voltage generating circuit; and 
 a control circuit connected to the first power supply line, the second power supply line, and the first ground line for generating the internal sleep mode signal in response to an external sleep mode signal and controlling a clock signal. 
 
   
   
     2. The leakage current control circuit with a single low voltage power supply of  claim 1 , wherein the leakage current control circuit enters into an active mode when the power transistor is turned on and enters into the sleep mode when the power transistor is turned off. 
   
   
     3. The leakage current control circuit with a single low voltage power supply of  claim 1 , wherein the power transistor has a low threshold voltage. 
   
   
     4. The leakage current control circuit with a single low voltage of  claim 3 , wherein the power transistor is a PMOS. 
   
   
     5. The leakage current control circuit with a single low voltage of  claim 1 , wherein the internal sleep signal controls the high-voltage generating circuit to turn on or off. 
   
   
     6. The leakage current control circuit with a single low voltage of  claim 1 , wherein the output of the high-voltage generating circuit is at a low level in the active mode and will be increased by a predetermined value in the sleep mode. 
   
   
     7. The leakage current control circuit with a single low voltage of  claim 6 , wherein the predetermined value is above the voltage of the said first power supply line. 
   
   
     8. The leakage current control circuit with a single low voltage of  claim 1 , wherein the control circuit controls the internal sleep mode signal and synchronizes the internal sleep mode signal with the external clock signal when entering into or getting out of the sleep mode. 
   
   
     9. The leakage current control circuit with a single low voltage of  claim 1 , wherein the internal sleep mode signal is activated after N clock cycles. 
   
   
     10. A leakage current control circuit with a single low voltage power supply, operating in a sleep mode or an active mode in response to an internal sleep mode signal, comprising:
 a first power supply line connected to a plurality of first components, the plurality of first components including one of a plurality of flip-flops and a plurality of combinational circuits; 
 a second power supply line connected to a plurality of second components, the plurality of second components including an other of the plurality of flip-flops and the plurality of combinational circuits, each of the plurality of first components and the plurality of second components being connected to different ones of the first and second power supply lines, respectively; 
 a first ground line; 
 a high-voltage generating circuit for generating an output voltage in response to the internal sleep mode signal; 
 a power transistor having a first end, a second end and a gate electrode, wherein the first end is connected to the said first power supply line, the second end is connected to the second power supply line, the gate electrode is connected to the output of the said high-voltage generating circuit; and 
 a control circuit connected to the first power supply line, the second power supply line, and the first ground line for generating the internal sleep mode signal in response to an external sleep mode signal and controlling a clock signal, wherein
 a clock signal oscillates between 0 voltage and power supply voltage in the active mode, and the output voltage of the high-voltage generating circuit is raised to a fixed voltage with a predetermined value in the sleep mode. 
 
 
   
   
     11. The leakage current control circuit with a single low voltage of  claim 10 , wherein the predetermined value is above the voltage of the first power supply line. 
   
   
     12. A leakage current control circuit with a single low voltage power supply, operating in a sleep mode or an active mode in response to an internal sleep mode signal, comprising:
 a first power supply line connected to a plurality of first components; 
 a first ground line connected to a plurality of first components, the plurality of first components including one of a plurality of flip-flops and a plurality of combinational circuits; 
 a second ground line connected to a plurality of second components, the plurality of second components including an other of the plurality of flip-flops and the plurality of combinational circuits, each of the plurality of first components and the plurality of second components being connected to only one of the respective first and second ground lines; 
 a low-voltage generating circuit for generating an output voltage in response to the internal sleep mode signal; 
 a power transistor having a first end, a second end and a gate electrode, wherein the first end is connected to the said first ground line, the second end is connected to the second ground line, the gate electrode is connected to the output of the said low-voltage generating circuit; and 
 a control circuit connected to the first power supply line, the first ground line and the second ground line for generating the internal sleep mode signal in response to an external sleep mode signal and controlling a clock signal. 
 
   
   
     13. The leakage current control circuit with a single low voltage of  claim 12 , wherein the leakage current control circuit enters into an active mode when the power transistor is turned on and enters into the sleep mode when the power transistor is turned off. 
   
   
     14. The leakage current control circuit with a single low voltage power supply of  claim 12 , wherein the power transistor has a low threshold voltage. 
   
   
     15. The leakage current control circuit with a single low voltage of  claim 12 , wherein the power transistor is a NMOS. 
   
   
     16. The leakage current control circuit with a single low voltage of  claim 12 , wherein the internal sleep signal controls the low-voltage generating circuit to turn on or off. 
   
   
     17. The leakage current control circuit with a single low voltage of  claim 12 , wherein the output of the low-voltage generating circuit is at a high level in the active mode and will be decreased by a predetermined value in the sleep mode. 
   
   
     18. The leakage current control circuit with a single low voltage of  claim 17 , wherein the predetermined value is below the voltage of the said first ground line. 
   
   
     19. The leakage current control circuit with a single low voltage of  claim 12 , wherein the control circuit controls the internal sleep mode signal and synchronizes the internal sleep mode signal with the external clock signal when entering into or getting out of the sleep mode. 
   
   
     20. The leakage current control circuit with a single low voltage of  claim 12 , wherein the internal sleep mode signal is activated after N clock cycles. 
   
   
     21. A leakage current control circuit with a single low voltage power supply, operating in a sleep mode or an active mode in response to an internal sleep mode signal, comprising:
 a first power supply line connected to a plurality of first components; 
 a first ground line connected to the plurality of first components, the plurality of first components including one of a plurality of flip-flops and a plurality of combinational circuits; 
 a second ground line connected to a plurality of second components, the plurality of second components including an other of the plurality of flip-flops and the plurality of combinational circuits, each of the plurality of first components and the plurality of second components being connected to only one of the respective first and second ground lines; 
 a low-voltage generating circuit for generating an output voltage in response to the internal sleep mode signal; 
 a power transistor having a first end, a second end and a gate electrode, wherein the first end is connected to the said first ground line, the second end is connected to the second ground line, the gate electrode is connected to the output of the said low-voltage generating circuit; and 
 a control circuit connected to the first power supply line, the first ground line and the second ground line for generating the internal sleep mode signal in response to an external sleep mode signal and controlling a clock signal, wherein
 a clock signal oscillates between 0 voltage and power supply voltage in the active mode, and the output voltage of the low-voltage generating circuit is lowered to a fixed voltage with a predetermined value in the sleep mode. 
 
 
   
   
     22. The leakage current control circuit with a single low voltage of  claim 21 , wherein the predetermined value is below the voltage of the first ground line. 
   
   
     23. A method for controlling a leakage current with a single low voltage power supply to respond to an internal sleep mode signal to make a circuit alternate between an active mode and a sleep mode, comprising:
 generating an output voltage higher than a power supply voltage in response to a sleep mode signal in the active mode, and outputting a clock signal in synchronization with the internal sleep mode signal to enter into the sleep mode; and 
 generating an output voltage at 0 level in response to a sleep mode signal in the sleep mode, and outputting a voltage of 0V; wherein
 in at least the active mode, each of a plurality of first components and a plurality of second components are supplied with a power supply voltage via first and second power supply lines, each of the plurality of first components and the plurality of second components being connected to different ones of the first and second power supply lines, respectively, 
 the plurality of first components including one of a plurality of flip-flops and a plurality of combinational circuits, and 
 the plurality of second components including an other of the plurality of flip-flops and the plurality of combinational circuits. 
 
 
   
   
     24. The method for controlling a leakage current with a single low voltage power supply of  claim 23 , wherein the output voltage generated by a high-voltage generating circuit is at low level in the active mode, and will be increased by a predetermined value in the sleep mode. 
   
   
     25. The method for controlling a leakage current with a single low voltage power supply of  claim 24 , wherein the predetermined value is above the voltage of the first power supply line. 
   
   
     26. The method for controlling a leakage current with a single low voltage power supply of  claim 23 , wherein the clock signal oscillates between the 0V and the power supply voltage in the active mode, and the output voltage will be increased by a predetermined value in the sleep mode. 
   
   
     27. The method for controlling a leakage current with a single low voltage power supply of  claim 26 , wherein the predetermined value is above the voltage of the first power supply line.