Lateral double-diffused MOSFET transistor with a lightly doped source

Abstract

Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described.

1. A transistor comprising:
 a p-type substrate; 
 a high voltage (HV) n-well formed in a surface area of the p-type substrate; 
 a source including:
 a p-doped p-body implanted in the HV n-well, 
 a p-doped p+ region within the p-body, 
 a first n-doped n+ region within the p-body and abutting the p+ region, the n+ region being on a side of the p-doped p+ region closer to the gate, and 
 a n-doped lightly doped source (N-LDS) region overlapping the first n-doped n+ region and extending laterally beneath a portion of the gate, 
 
 a drain including a second n-doped n+ region; and 
 a gate to control a depletion region between the source and the drain, 
 wherein the n-doped lightly doped source is implanted only in the source and not in the drain. 
 
   
   
     2. The transistor of  claim 1 , wherein the drain further comprises an n-doped shallow drain, the second n-doped n+ region being within the n-doped shallow drain. 
   
   
     3. The transistor of  claim 2 , wherein the second n+ region extends deeper than the n-doped shallow drain. 
   
   
     4. The transistor of  claim 2 , wherein the second n-doped n+ region is self-aligned to the gate of the transistor. 
   
   
     5. The transistor of  claim 1 , wherein the first n+ region is surrounded by the p-body. 
   
   
     6. The transistor of  claim 1 , wherein the p-body is deeper than the p+ region, the first n+ region and the N-LDS region. 
   
   
     7. The transistor of  claim 1 , wherein the gate includes a gate oxide between the source and the drain, and wherein the N-LDS extend beneath the gate oxide. 
   
   
     8. The transistor of  claim 7 , wherein the N-LDS region extends further laterally beneath the gate oxide than the n+ region. 
   
   
     9. The transistor of  claim 7 , wherein the n-doped shallow drain extends beneath the gate oxide. 
   
   
     10. The transistor of  claim 9 , wherein an outer boundary of the n-doped shallow drain extends further laterally beneath the gate oxide toward the source than an outer boundary of the second n-doped n+ region. 
   
   
     11. The transistor of  claim 1 , wherein the p-doped body is self-aligned to the gate of the transistor. 
   
   
     12. The transistor of  claim 1 , wherein the n-doped shallow drain is self-aligned to the gate of the transistor. 
   
   
     13. The transistor of  claim 7 , wherein the gate oxide is covered with a conductive material. 
   
   
     14. The transistor of  claim 1 , wherein an outer boundary of the n-doped lightly doped source is aligned with an outer boundary of the first n-doped n+ region. 
   
   
     15. The transistor of  claim 1 , wherein the n-doped lightly doped source is adjacent to and abuts the p+ region. 
   
   
     16. The transistor of  claim 7 , wherein a bottom surface of the gate oxide is substantially flat. 
   
   
     17. The transistor of  claim 13 , where the gate oxide separates the conductive material from the p-type substrate.