Amplification-type CMOS image sensor

Abstract

Pixels are two-dimensionally arranged into rows and columns in an image sensing region of a solid-state image sensing device, and divided into a plurality of vertical blocks. A vertical signal line is connected to each pixel column. A voltage read out from a pixel is A/D-converted and held in a holding circuit. A vertical block selection circuit outputs a vertical block selection signal in response to a horizontal sync pulse. An intra-block line selection circuit selects one pixel row in one block or simultaneously selects a plurality of pixel rows in one block, in accordance with the selection signal and a signal for setting the number of lines to be selected. A pulse selector circuit supplies a pixel driving pulse signal to a pixel row selected by the intra-block line selection circuit.

1. A solid-state image sensing device comprising:
 an image sensing region in which pixels are two-dimensionally arranged into rows and columns on a semiconductor substrate, the pixel comprising a photoelectric conversion circuit configured to convert an optical signal into a signal charge and store the signal charge, a read circuit configured to read out the electric charge stored in the photoelectric conversion circuit to a detecting portion, an amplification circuit configured to amplify and output a voltage corresponding to an amount of electric charge in the detecting portion, and a reset circuit configured to reset the electric charge in the detecting portion; 
 a vertical signal line connected to each pixel column in the image sensing region; 
 a variable load circuit connected to the vertical signal line, and configured to increase an electric current flowing through the vertical signal line when a plurality of pixel rows are simultaneously selected; and 
 a storage circuit configured to hold the voltage read out to the vertical signal line from each amplification circuit in a selected pixel row, 
 wherein the image sensing region includes a plurality of vertical blocks where the pixels are two-dimensionally arranged, the solid-state image sensing device further comprises:
 a vertical block selection circuit configured to output a vertical block selection signal in response to a horizontal sync pulse; 
 an intra-block line selection circuit which selects one pixel row in one vertical block or simultaneously selects a plurality of pixel rows in one vertical block, on the basis of the vertical block selection signal output from the vertical block selection circuit, and a signal for setting the number of lines to be selected; and 
 a pulse selector circuit configured to supply a pulse signal to a pixel row selected by the intra-block line selection circuit, on the basis of an output signal from the intra-block line selection circuit and a pixel driving pulse signal. 
 
 
     
     
       2. A solid-state image sensing device according to  claim 1 , wherein the variable load circuit comprises load transistors each having a current path connected between the vertical signal line and a ground point, and a bias circuit configured to apply a first bias voltage and a second bias voltage to a gate of each load transistor, and the bias circuit applies the first bias voltage to the gate of each load transistor in a normal operation, and applies the second bias voltage higher than the first bias voltage to decrease a conduction resistance of the load transistor when a plurality of pixel rows are simultaneously selected, thereby increasing an amount of electric current flowing through the vertical signal line. 
     
     
       3. A solid-state image sensing device according to  claim 1 , wherein the variable load circuit comprises a first load transistor whose current path is connected between the vertical signal line and a ground point, a second load transistor whose current path is connected in parallel to the first load transistor, and a bias circuit configured to selectively apply a bias voltage to gates of the first load transistor and the second load transistor, and the bias circuit applies the bias voltage to the gate of the first load transistor to turn on the first load transistor in a normal operation, and applies the bias voltage to the gates of the first load transistor and the second load transistor to turn on the first load transistor and the second load transistor when a plurality of pixel rows are simultaneously selected, thereby increasing an amount of electric current flowing through the vertical signal line. 
     
     
       4. A solid-state image sensing device according to  claim 1 , further comprising:
 an analog-to-digital conversion circuit configured to perform analog-to-digital conversion on the voltage read out to the vertical signal line from each amplification circuit in the selected pixel row; 
 a holding circuit configured to hold digital data obtained by the analog-to-digital conversion circuit; and 
 a switch addition circuit formed between the image sensing region and the analog-to-digital conversion circuit, and configured to connect a plurality of vertical signal lines to an input terminal of the analog-to-digital conversion circuit and add data read out from a plurality of pixels. 
 
     
     
       5. A solid-state image sensing device according to  claim 4 , wherein
 the switch addition circuit comprises a first synthesizing switch whose current path is connected between the vertical signal line and an input terminal of the analog-to-digital conversion circuit, and a second synthesizing switch whose current path is connected between the vertical signal line and an input terminal, which is different from the input terminal connected to the first synthesizing switch, of the analog-to-digital conversion circuit, and 
 when the second synthesizing switch is turned on, a portion of the analog-to-digital conversion circuit connected to the second synthesizing switch is stopped. 
 
     
     
       6. A solid-state image sensing device according to  claim 1 , wherein the storage circuit comprises a column-type noise canceling circuit, an analog-to-digital converter, a latch circuit which latches a signal having undergone analog-to-digital conversion by the analog-to-digital converter, a line memory which stores the signal latched by the latch circuit, and a horizontal shift register circuit which reads out the signal from the line memory.