Pre-patterned thin film capacitor and method for embedding same in a package substrate

Abstract

An embedded passive structure, its method of formation, and its integration onto a substrate during fabrication are disclosed. In one embodiment, the embedded passive structure is a thin film capacitor (TFC) formed using a thin film laminate that has been mounted onto a substrate. The TFC's capacitor dielectric and/or lower electrode layers are patterned in such a way as to reduce damage and improve cycle time. In one embodiment, the capacitor dielectric has a high dielectric constant and the substrate is an organic packaging substrate.

1. A method for forming embedded passive structures in an organic packaging substrate comprising:
 affixing an embedded passive laminate on the organic packaging substrate, wherein the embedded passive laminate being affixed includes a pre-patterned capacitor dielectric layer having a first opening, and wherein a conductive layer of the affixed embedded passive laminate covers the first opening; and 
 after the affixing,
 removing a portion of the conductive layer to expose the first opening, and 
 forming a via opening through the exposed first opening to the organic packaging substrate. 
 
 
   
   
     2. The method of  claim 1 , wherein the pre-patterned capacitor dielectric layer is further characterized as a ceramic dielectric material. 
   
   
     3. The method of  claim 2 , wherein the ceramic dielectric material is further characterized as being selected from a group consisting of strontium titinate, barium strontium titinate, and/or barium titinate. 
   
   
     4. The method of  claim 3 , wherein the substrate is further characterized as an organic substrate. 
   
   
     5. A method for forming an embedded thin film capacitor comprising:
 forming a thin film capacitor laminate, including
 depositing a ceramic dielectric layer over a base layer of conductive material, 
 patterning the ceramic dielectric layer to form first openings to portions of the base layer, 
 depositing a lower electrode layer over the ceramic dielectric layer, and 
 patterning the lower electrode layer to form second openings to portions of the base layer, 
 
 the formed thin film capacitor laminate having a combination of the base layer, the patterned ceramic dielectric layer, and the patterned lower electrode layer; 
 mounting the formed thin film capacitor laminate over a second dielectric layer on a substrate, wherein the patterned lower electrode layer is positioned between the base layer and the second dielectric layer; and 
 removing a portion of the base layer from the mounted thin film capacitor laminate to expose one of the formed first openings; 
 forming on the mounted thin film capacitor laminate a via opening through the exposed one of the first openings to one of the formed second openings, the formed via opening extending through the second dielectric layer to an underlying conductive structure. 
 
   
   
     6. The method of  claim 5  further comprising heating the ceramic dielectric at a temperature in a range of 500-900 degrees Celsius prior to depositing the lower electrode layer. 
   
   
     7. The method of  claim 5 , the method further comprising:
 filling the via openings with a conductive material; and 
 patterning the conductive material to form a conductive structure. 
 
   
   
     8. The method of  claim 5 , wherein the ceramic dielectric layer includes a material selected from a group consisting of strontium titinate, barium strontium titinate, and/or barium titinate. 
   
   
     9. The method of  claim 5 , wherein the base layer includes at least one of copper and nickel. 
   
   
     10. The method of  claim 5 , wherein the lower electrode layer includes at least one of copper, platinum, and nickel. 
   
   
     11. The method of  claim 5 , wherein the first opening is wider than the second opening. 
   
   
     12. The method of  claim 5 , wherein the second opening is wider than the first opening and wherein the conductive structure electrically couples to portions of the lower electrode layer. 
   
   
     13. The method of  claim 5 , wherein the conductive structure is further characterized as an upper capacitor electrode.