Vertical channel transistor in semiconductor device and method of fabricating the same

Abstract

A method of fabricating a vertical channel transistor for a semiconductor device includes forming, on a substrate, a plurality of active pillars each having a gate electrode formed on and surrounding a lower portion thereof; forming a first insulation layer over the active pillars to fill a gap region between the active pillars; partially removing the first insulation layer to exposes a circumferential surface of the gate electrode in all directions, without exposing the substrate in the gap region between the active pillars; forming a conductive layer on the remaining first insulation layer to fill the gap region between the active pillars; and patterning the conductive layer to form a word line that surrounds and contacts the circumferential surface of the gate electrode in all directions.

1. A method of fabricating a vertical channel transistor for a semiconductor device, the method comprising:
 forming, on a substrate, a plurality of active pillars each having a gate electrode formed on and surrounding a lower portion thereof; 
 forming a first insulation layer over the active pillars to fill a gap region between the active pillars; 
 partially removing the first insulation layer to exposes a circumferential surface of the gate electrode in all directions, without exposing the substrate in the gap region between the active pillars; 
 forming a conductive layer on the remaining first insulation layer to fill the gap region between the active pillars; and 
 patterning the conductive layer to form a word line that surrounds and contacts the circumferential surface of the gate electrode in all directions. 
 
   
   
     2. The method of  claim 1 , wherein the patterning comprises:
 forming a mask pattern covering at least a line of the active pillars on a resultant structure after the conductive layer has been formed; and 
 forming the word line by etching the conductive layer using the mask pattern as an etch mask. 
 
   
   
     3. The method of  claim 2 , wherein a width of the mask pattern is larger than a diameter of the active pillars being covered by the mask pattern. 
   
   
     4. The method of  claim 2 , wherein the forming of the word line further includes:
 performing an etch-back process on the patterned conductive layer to a level of an upper part of the gate electrode. 
 
   
   
     5. The method of  claim 4 , wherein the etch-back process is performed on the patterned conductive layer by:
 forming a second insulation layer over a resultant structure after the conductive layer has been patterned; 
 performing an etch-back process on the second insulation layer to the level of the upper part of the gate electrode; and 
 etching the patterned conductive layer to the level of the upper part of the gate electrode. 
 
   
   
     6. The method of  claim 1 , wherein the partially removing of the first insulation layer includes
 performing an etch-back process on the first insulation layer without using any etch mask. 
 
   
   
     7. The method of  claim 6 , wherein the etch-back process is performed by using a wet-etching process. 
   
   
     8. The method of  claim 1 , wherein the partially removing of the first insulation layer is performed, regardless of any etching profile, under a high etch selectivity of the first insulation layer with respect to a hard mask nitride layer formed over an upper portion of each of the active pillars. 
   
   
     9. The method of  claim 1 , further comprising, before the patterning:
 planarizing the conductive layer until a hard mask layer formed over an upper portion of each of the active pillars is exposed. 
 
   
   
     10. The method of  claim 1 , further comprising, before the patterning:
 planarizing the conductive layer without exposing a hard mask layer formed over an upper portion of each of the active pillars. 
 
   
   
     11. The method of  claim 1 , wherein the conductive layer includes any one of a polysilicon and a metal. 
   
   
     12. The method of  claim 1 , wherein the gate electrode includes any one of a polysilicon and a metal. 
   
   
     13. The method of  claim 1 , wherein the first insulation layer includes an oxide layer. 
   
   
     14. A method of fabricating a vertical channel transistor on a substrate having thereon a plurality of active pillars each having a gate electrode formed on and surrounding a lower portion thereof, the method comprising:
 forming an insulation layer over the active pillars to fill a gap region between the active pillars; 
 partially removing the insulation layer to expose, in full 360 degrees, a circumferential surface of the gate electrode, without exposing the substrate in the gap region between the active pillars; and 
 forming a word line that surrounds and contacts the circumferential surface of the gate electrode in full 360 degrees. 
 
   
   
     15. The method of  claim 14 , wherein the partially removing comprises:
 performing an etch-back process on the insulation layer without using any etch mask. 
 
   
   
     16. The method of  claim 15 , wherein the etch-back process comprises a wet-etching process. 
   
   
     17. The method of  claim 14 , wherein the partially removing of the insulation layer is performed, regardless of any etching profile, under a high etch selectivity of the insulation layer with respect to a hard mask layer formed over an upper portion of each of the active pillars.