Insulated gate silicon carbide semiconductor device and method for manufacturing the same

Abstract

An insulated gate silicon carbide semiconductor device is provided having small on-resistance in a structure obtained by combining the SIT and MOSFET structures having normally-off operation. The device includes an n − semiconductor layer on an SiC n + substrate, a p-type base region and highly doped p-region both buried in the layer, a trench from the semiconductor layer surface to the p-base region, an n + first source region in the surface of a p-type base region at the bottom of the trench, a p-type channel region in the surface of the sidewall of the trench, one end of which contacts the first source region, a gate electrode contacting the trench-side surface of the channel region via a gate insulating film, and a source electrode contacting the trench-side surface of the gate electrode via an interlayer insulating film and contacting the exposed first source region and p-base region at the bottom of the trench.

1. An insulated gate silicon carbide semiconductor device primarily made of silicon carbide semiconductor material, the semiconductor device comprising:
 a first conduction-type low-concentration deposition semiconductor layer deposited on a first conduction-type high-concentration semiconductor substrate; 
 a second conduction-type base region buried in the first conduction-type low-concentration deposition semiconductor layer; 
 a trench extending from the surface of the first conduction-type low-concentration deposition semiconductor layer to the second conduction-type base region; 
 a first conduction-type first source region selectively formed in the surface layer of the second conduction-type base region at the bottom of the trench; 
 a second conduction-type channel region formed in a surface layer of the first conduction-type low-concentration deposition semiconductor layer along a sidewall of the trench, wherein one end of the second conduction-type channel region is in contact with the first conduction-type first source region; 
 a gate electrode located adjacent to the second conduction-type channel region formed along the sidewall of the trench, wherein a gate insulating film is provided between the gate electrode and the second conduction-type channel region; 
 a source electrode located adjacent to the gate electrode on the trench sidewall, wherein an interlayer insulating film is provided between the source electrode and the gate electrode, and wherein the source electrode is in direct contact with a surface of the first conduction-type first source region and a surface of the second conduction-type base region that are exposed at the bottom of the trench; and 
 a drain electrode on the opposite side of the semiconductor substrate from the source electrode. 
 
     
     
       2. The insulated gate silicon carbide semiconductor device according to  claim 1 , wherein the gate electrode does not extend over the surface of the first conduction-type low-concentration deposition semiconductor layer. 
     
     
       3. The insulated gate silicon carbide semiconductor device according to  claim 1  further comprising a first conduction-type high-concentration second source region in the surface layer of the first conduction-type low-concentration deposition semiconductor layer adjacent to the trench. 
     
     
       4. The insulated gate silicon carbide semiconductor device according to  claim 3 , wherein the gate electrode extends over the second source region. 
     
     
       5. An insulated gate silicon carbide semiconductor device primarily made of silicon carbide semiconductor material, the semiconductor device comprising:
 a first conduction-type low-concentration deposition semiconductor layer deposited on a first conduction-type high-concentration semiconductor substrate; 
 a second conduction-type base region buried in the first conduction-type low-concentration deposition semiconductor layer; 
 a trench extending from the surface of the first conduction-type low-concentration deposition semiconductor layer to the second conduction-type base region; 
 a first conduction-type first source region selectively formed in the surface layer of the second conduction-type base region at the bottom of the trench; 
 a first conduction-type high-concentration second source region formed in the surface layer of the first conduction-type low-concentration deposition semiconductor layer adjacent to the trench: 
 a second conduction-type channel region formed in a surface layer of the first conduction-type low-concentration deposition semiconductor layer along a sidewall of the trench, wherein one end of the second conduction-type channel region is in contact with the first conduction-type first source region; 
 a gate electrode located adjacent to the second conduction-type channel region formed along the sidewall of the trench, wherein a gate insulating film is provided between the gate electrode and the second conduction-type channel region; and 
 a source electrode located adjacent to the gate electrode on the trench sidewall, wherein an interlayer insulating film is provided between the source electrode and the gate electrode, and wherein the source electrode is in contact with a surface of the first conduction-type first source region and a surface of the second conduction-type base region that are exposed at the bottom of the trench, 
 wherein the second conduction-type base region has a two-layer configuration including a deep high-concentration first base region and a shallow low-concentration second base region. 
 
     
     
       6. The insulated gate silicon carbide semiconductor device according to  claim 5  further comprising a contact trench at the bottom of the trench, the contact trench reaching the first base region, wherein the source electrode is in contact with the contact trench.