Ultra slim semiconductor package and method of fabricating the same

Abstract

There is provided an ultra slim semiconductor package comprising: a multilayer thin film layer including at least one or more dielectric layers and at least one or more redistribution layers; at least one semiconductor chip electrically connected to the redistribution layer and mounted on the multilayer thin film layer; conductive structures electrically connected to the redistribution layer and each formed in a post shape at one side of the multilayer thin film layer; a molding part formed on the multilayer thin film layer and at least partially covering the conductive structures and the semiconductor chip; and bumps for external connection formed on the molding part and electrically connected to the conductive structures. The semiconductor package according to the present invention enables mass production at wafer level, is easily stacked between the packages, and has an excellent electrical characteristic. Further, since the package thickness is very thin, the semiconductor package contributes to the slimming of diverse electronic products.

1. An ultra slim semiconductor package comprising:
 a multilayer thin film layer including a first dielectric layer, a first redistribution layer on the first dielectric layer, and a second dielectric layer on the first redistribution layer; 
 at least one semiconductor chip electrically connected to the first redistribution layer and mounted on the multilayer thin film layer; 
 conductive structures electrically connected to the first redistribution layer and each formed in a post shape at one side of the multilayer thin film layer; 
 a molding part formed on the multilayer thin film layer and at least partially covering the conductive structures and the semiconductor chip; 
 a second redistribution layer on the top side of the molding part; 
 a third second dielectric layer directly formed on the second redistribution layer; 
 bumps for external connection formed on the molding part and electrically connected to the conductive structures through the second redistribution layer, 
 wherein the bumps are adapted to be mounted on a circuit board, the bumps extending below a lowermost surface of the third dielectric layer; 
 wherein substantially all of the bumps are disposed such that they do not overlap with a top side of the semiconductor chip; 
 wherein the top side of the molding part has the same height as the top side of the semiconductor chip; and 
 wherein, at one side of the semiconductor chip, a heat spreader is positioned between the bumps for external connection. 
 
     
     
       2. The ultra slim semiconductor package of  claim 1 , wherein the semiconductor chip is electrically connected to the multilayer thin film layer by additional solder bumps. 
     
     
       3. The ultra slim semiconductor package of  claim 2 , wherein the solder bumps are electrically connected to the conductive structures of the multilayer thin film layer through the first redistribution layer. 
     
     
       4. The ultra slim semiconductor package of  claim 1 , wherein the multilayer thin film layer comprises a thin film passive device. 
     
     
       5. The ultra slim semiconductor package of  claim 1 , further comprising:
 another semiconductor package to be stacked on or under the semiconductor package. 
 
     
     
       6. The ultra slim semiconductor package of  claim 5 , wherein the two stacked semiconductor packages are electrically connected to each other by the bumps for external connection, and the bumps for external connection of the two packages are different in size. 
     
     
       7. The ultra slim semiconductor package of  claim 1 , wherein two or more semiconductor chips are electrically connected to the first redistribution layer and are mounted on the multilayer thin film layer, and the semiconductor chips are arranged to each other horizontally or vertically. 
     
     
       8. The ultra slim semiconductor package of  claim 1 , wherein the first redistribution layer and the second redistribution layer are symmetrically placed at both side of the molding part. 
     
     
       9. The ultra slim semiconductor package of  claim 1 , wherein the conductive structure has a tapered portion extending above the molding part and extending through the first dielectric layer. 
     
     
       10. The ultra slim semiconductor package of  claim 1 , wherein the package contains only a single semiconductor chip therein.