Test interposer having active circuit component and method therefor

Abstract

A device under test (DUT) is tested via a test interposer. The test interposer includes a first set of contacts at a first surface to interface with the contacts of a load board or other interface of an automated test equipment (ATE) and a second set of contacts at an opposing second surface to interface with the contacts of the DUT. The second set of contacts can have a smaller contact pitch than the contact pitch of the first set of contacts to facilitate connection to the smaller pitch of the contacts of the DUT. The test interposer further includes one or more active circuit components or passive circuit components to facilitate testing of the DUT. The test interposer can be implemented as an integrated circuit (IC) package that encapsulates the circuit components.

1. A system comprising:
 a test interposer comprising:
 an integrated circuit package comprising:
 a first surface and a second surface; 
 a first array of contacts disposed at the first surface, each contact of the first array of contacts configured to electrically connect to a corresponding contact of a second array of contacts of a load board, the load board coupled to a testing equipment; 
 a third array of contacts disposed at the second surface, each contact of the third array of contacts configured to electrically connect to a corresponding contact of a fourth array of contacts of a device under test (DUT); 
 a first die; 
 a second die separate from the first die; 
 an active circuit component disposed at the first die, the active circuit component coupled to a first contact of the first array of contacts and a second contact of the third array of contacts; and 
 an encapsulant overlying the first die, the second die, and the active circuit component. 
 
 
 
     
     
       2. The system of  claim 1 , wherein the active circuit component comprises one selected from a group consisting of: a memory component; a microprocessor component; a digital signal processor component; an analog-to-digital (A/D) converter; an application specific integrated circuit (ASIC); and a field programmable logic array (FPGA). 
     
     
       3. The system of  claim 1 , wherein:
 the first array of contacts is arranged to have a first contact pitch; and 
 the third array of contacts is arranged to have a second contact pitch, the second contact pitch smaller than the first contact pitch. 
 
     
     
       4. The system of  claim 1 , further comprising:
 the load board; and 
 the DUT. 
 
     
     
       5. The system of  claim 1 , wherein the third array of contacts comprises one selected from a group consisting of: an array of metal bumps; an array of metal balls; an array of metal columns; an array of recessed contacts; an array of micro-electrical-mechanical system (MEMS) probes; and an array of metal-filled columns. 
     
     
       6. The system of  claim 1 , wherein:
 the first die comprises a set of die pads disposed at a surface of the first die; and 
 the test interposer further comprises an interconnects to connect a die pad of the set of die pads to at least one of a contact of the first array of contacts or a contact of the third array of contacts. 
 
     
     
       7. The system of  claim 1 , wherein the active circuit component implements at least one of: a signal amplification function; a signal filtering function; a signal resampling function; a dejittering function; a data storage function; a clock generation function; and a phase alignment function. 
     
     
       8. The system of  claim 1 , wherein the encapsulant comprises an epoxy molding compound. 
     
     
       9. A method comprising:
 providing a load board and a test interposer, the load board comprising a first array of contacts and the test interposer comprising an integrated circuit package having a first surface facing the first array of contacts of the load board and a second surface facing a second array of contacts of a device under test (DUT), the test interposer further comprising a third array of contacts electrically connected to the first array of contacts of the load board and a fourth array of contacts electrically connected to the second array of contacts of the DUT, and the integrated circuit package having a first die and a second die separate from the first die, an active circuit component disposed at the first die, and an encapsulant overlying the first die, the second die, and the active circuit component, the active circuit component coupled to a first contact of the third array of contacts and to a second contact of the fourth array of contacts; and 
 testing the DUT via signaling conducted between the load board and the DUT via the test interposer. 
 
     
     
       10. The method of  claim 9 , wherein:
 testing the DUT comprises controlling an operation of the active circuit component based on signaling received at the test interposer via at least one of the first contact and the second contact. 
 
     
     
       11. The method of  claim 9 , wherein:
 providing the load board and the test interposer comprises providing the test interposer comprising a passive circuit component encapsulated the integrated circuit package, the passive circuit component coupled to a third contact of the third array of contacts and to a fourth contact of the fourth array of contacts; and 
 testing the DUT comprises conducting signaling between the third contact and the fourth contact via the passive circuit component. 
 
     
     
       12. The method of  claim 9 , wherein providing the test interposer comprises providing the test interposer having the fourth array of contacts arranged to have a first contact pitch the third array of contacts arranged to have a second contact pitch, the second contact pitch smaller than the first contact pitch. 
     
     
       13. The method of  claim 9 , wherein providing the test interposer comprises fabricating the test interposer using a Redistributed Chip Packaging (RCP) process. 
     
     
       14. The method of  claim 9 , wherein testing the DUT comprises operating the active circuit component to perform least one of: a signal amplification function; a signal filtering function; a signal resampling function; a dejittering function; a data storage function; a clock generation function; and a phase alignment function. 
     
     
       15. An electronic device testing system comprising:
 a load board comprising a first array of contacts; 
 a device under test (DUT) comprising a second array of contacts; and 
 a test interposer comprising:
 an integrated circuit package comprising:
 a first surface and a second surface, the first surface facing the first array of contacts and the second surface facing the second array of contacts; 
 a third array of contacts disposed at the first surface, each contact of the third array of contacts electrically coupled to a corresponding contact of the first array of contacts; 
 a fourth array of contacts disposed at the second surface, each contact of the fourth array of contacts electronically coupled to a corresponding contact of the second array of contacts; 
 a first die; 
 a second die separate from the first die; 
 an active circuit component disposed at the first die and coupled to a first contact of the third array of contacts and to a second contact of the fourth array of contacts; and 
 an encapsulant overlying the first die, the second die, and the active circuit component. 
 
 
 
     
     
       16. The electronic device testing system of  claim 15 , wherein the fourth array of contacts comprises one selected from a group consisting of: an array of metal bumps; an array of metal balls; an array of metal columns; an array of recessed contacts; an array of micro-electrical-mechanical system (MEMS) probes; and an array of metal-filled columns. 
     
     
       17. The electronic device testing system of  claim 15 , wherein the active circuit component comprises one selected from a group consisting of: a memory component; a microprocessor component; a digital signal processor component; an analog-to-digital (A/D) converter; an application specific integrated circuit (ASIC); and a field programmable logic array (FPGA). 
     
     
       18. The electronic device testing system of  claim 15 , wherein:
 the third array of contacts is arranged to have a first contact pitch; and 
 the fourth array of contacts is arranged to have a second contact pitch, the second contact pitch smaller than the first contact pitch. 
 
     
     
       19. The electronic device testing system of  claim 15 , wherein:
 the first die comprises a set of die pads disposed at a surface of the first die; and 
 the test interposer further comprises an interconnects to connect a die pad of the set of die pads to at least one of a contact of the first array of contacts or a contact of the third array of contacts. 
 
     
     
       20. The electronic device testing system of  claim 15 , wherein the encapsulant comprises an epoxy molding compound.