P
US7879672B2ActiveUtilityPatentIndex 60

eDRAM memory cell structure and method of fabricating

Assignee: IBMPriority: Feb 23, 2009Filed: Feb 23, 2009Granted: Feb 1, 2011
Est. expiryFeb 23, 2029(~2.6 yrs left)· nominal 20-yr term from priority
Inventors:CHENG KANGGUOKIM BYEONG YEOLNORUM JAMES PATRICK
H10D 86/01H10D 86/201H10B 12/37H10B 12/0387
60
PatentIndex Score
2
Cited by
3
References
8
Claims

Abstract

A deep trench structure process for forming a deep trench in a silicon on insulator (SOI) substrate. The SOI substrate has a bulk silicon layer, a buried oxide (BOX) layer and an SOI layer. In the process, the trench fill is recessed only to a level within the SOI layer so as to avoid lateral etching of the BOX layer. The buried strap is then formed followed by the STI oxide.

Claims

exact text as granted — not AI-modified
1. A method for forming an eDRAM memory cell structure comprising the steps of:
 forming a trench in a silicon on insulator (SOI) substrate comprising a bulk silicon layer, a buried oxide (BOX) layer and an SOI layer, the trench formed to a depth extending through the SOI layer and the BOX layer of the SOI substrate; 
 forming a node dielectric in the trench; 
 filling the trench with a first fill material; 
 recessing the first fill material to a level within the SOI layer; 
 recessing the node dielectric to form a divot; 
 filling the divot and forming a buried strap on the first fill material for making an electrical connection between the SOI layer and first fill material; 
 filling the trench with a second fill material; and 
 forming a gate on the SOI layer and a passing wordline on the second fill material. 
 
     
     
       2. The method of  claim 1  further comprising the step of avoiding etching the BOX layer during the steps of recessing the first fill material and recessing the node dielectric. 
     
     
       3. The method of  claim 1  further comprising a second trench adjacent to the trench and wherein the BOX layer between the trench and the second trench is not laterally etched during the steps of recessing the first fill material and recessing the node dielectric. 
     
     
       4. The method of  claim 1  wherein the first and second fill materials comprise doped polysilicon. 
     
     
       5. The method of  claim 1  wherein the step of recessing the node dielectric is recessing the node dielectric to a level within the SOI layer. 
     
     
       6. The method of  claim 1  wherein the step of filling the divot and forming a buried strap is by a conformal deposition process. 
     
     
       7. The method of  claim 1  wherein the step of filling the divot and forming a buried strap includes forming the buried strap in the divot. 
     
     
       8. The method of  claim 1  wherein forming a buried strap includes removing a portion of the buried strap and underlying first fill material prior to filling the trench with a second fill material.

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