Method of forming a semiconductor structure

Abstract

Disclosed is semiconductor structure that incorporates a field shield below a semiconductor device (e.g., a field effect transistor (FET) or a diode). The field shield is sandwiched between upper and lower isolation layers on a wafer. A local interconnect extends through the upper isolation layer and connects the field shield to a selected doped semiconductor region of the device (e.g., a source/drain region of a FET or a cathode or anode of a diode). Current that passes into the device, for example, during back-end of the line charging, is shunted by the local interconnect away from the upper isolation layer and down into the field shield. Consequently, an electric charge is not allowed to build up in the upper isolation layer but rather bleeds from the field shield into the lower isolation layer and into the substrate below. This field shield further provides a protective barrier against any electric charge that becomes trapped within the lower isolation layer or substrate.

1. A method of forming a semiconductor structure, said method comprising:
 providing a wafer comprising a substrate, a first isolation layer on said substrate, a conductive layer on said first isolation layer, a second isolation layer on said conductive layer and a semiconductor layer on said second isolation layer; 
 etching a trench in said wafer through said semiconductor layer to said first isolation layer so as to form a stack on said first isolation layer; 
 forming a spacer adjacent to a sidewall of said stack; 
 after said forming of said spacer, filling said trench with a dielectric material; 
 selectively removing said spacer to create an opening adjacent to said sidewall; 
 depositing a conductor into said opening; and 
 forming a semiconductor device above said second isolation layer, wherein said forming of said semiconductor device comprises forming, adjacent to said conductor, a doped semiconductor region. 
 
     
     
       2. The method of  claim 1 , wherein said forming of said semiconductor device comprises forming a field effect transistor and wherein said forming of said doped semiconductor region comprises forming, within said semiconductor layer, source/drain regions such that one of said source/drain regions is adjacent to said conductor. 
     
     
       3. The method of  claim 1 , wherein said forming of said semiconductor device comprises forming a diode and wherein said forming of said doped semiconductor region comprises forming, within said semiconductor layer, an anode and a cathode such that one of said anode and said cathode is adjacent to said conductor. 
     
     
       4. The method of  claim 1 , further comprising forming a metal strap connecting said conductor and said doped semiconductor region. 
     
     
       5. A method of forming a semiconductor structure, said method comprising:
 providing a wafer comprising a substrate, a first isolation layer on said substrate, a conductive layer on said first isolation layer, a second isolation layer on said conductive layer and a semiconductor layer on said second isolation layer; 
 etching a trench in said wafer through said semiconductor layer to said first isolation layer so as to form a stack on said first isolation layer; 
 forming a spacer adjacent to a sidewall of said stack, wherein said spacer comprises a conductor; 
 after said forming of said spacer, filling said trench with a dielectric material; and 
 forming a device above said second isolation layer, wherein said forming of said device comprises forming, adjacent to said conductor, a doped semiconductor region. 
 
     
     
       6. The method of  claim 5 , wherein said forming of said device comprises forming a field effect transistor and wherein said forming of said doped semiconductor region comprises forming, within said semiconductor layer, source/drain regions such that one of said source/drain regions is adjacent to said conductor. 
     
     
       7. The method of  claim 5 , wherein said forming of said device comprises forming a diode and wherein said forming of said doped semiconductor region comprises forming, within said semiconductor layer, an anode and a cathode such that one of said anode and said cathode is adjacent to said conductor. 
     
     
       8. The method of  claim 5 , further comprising forming a metal strap adjacent to said conductor and said doped semiconductor region. 
     
     
       9. A method of forming a semiconductor structure, said method comprising:
 providing a wafer comprising a substrate, a first isolation layer on said substrate, a conductive layer on said first isolation layer, a second isolation layer on said conductive layer and a semiconductor layer on said second isolation layer; 
 etching a trench in said wafer through said semiconductor layer to said first isolation layer so as to form a stack on said first isolation layer; 
 forming a spacer adjacent to a sidewall of said stack; 
 after said forming of said spacer, filling said trench with a dielectric material; 
 selectively removing said spacer to create an opening adjacent to said sidewall; 
 depositing a conductor into said opening; and 
 forming a semiconductor device above said second isolation layer, wherein said forming of said semiconductor device comprises forming, adjacent to said conductor, a doped semiconductor region, wherein said forming of said semiconductor device comprises forming a field effect transistor and wherein said forming of said doped semiconductor region comprises forming, within said semiconductor layer, source/drain regions such that one of said source/drain regions is adjacent to said conductor. 
 
     
     
       10. The method of  claim 9 , wherein said forming of said semiconductor device comprises forming a diode and wherein said forming of said doped semiconductor region comprises forming, within said semiconductor layer, an anode and a cathode such that one of said anode and said cathode is adjacent to said conductor. 
     
     
       11. The method of  claim 9 , further comprising forming a metal strap connecting said conductor and said doped semiconductor region.