Planarization method in the fabrication of a circuit

Abstract

Planarization methods for maintaining planar surfaces in the fabrication of such devices as BAW devices and capacitors on a planar or planarized substrate are described. In accordance with the method, a metal layer is deposited and patterned, and an oxide layer is deposited using a high density plasma chemical vapor deposition (HDP CVD) process to a thickness equal to the thickness of the metal layer. The HDP CVD process provides an oxide layer on the patterned metal tapering upward from the edge of the patterned metal layer. Then, after masking and etching the oxide layer from the patterned metal layer, the patterned metal layer and surrounding oxide layer form a substantially planar layer, interrupted by small remaining oxide protrusions at the edges of the patterned layer. These small remaining oxide protrusions may be too small to significantly disturb the flatness of a further oxide or other layer or they may be further mitigated by the application of another HDP CVD oxide film.

1. In the fabrication of a circuit, a method of maintaining a planar surface on an oxide layer deposited over a patterned layer of metal on a substrate comprising:
 depositing a dielectric layer on the substrate; 
 depositing and patterning the metal layer on the dielectric layer; 
 depositing a first oxide layer over the patterned layer of metal and the dielectric layer using high density plasma chemical vapor deposition (HDP CVD) to a thickness substantially equal to the thickness of the metal layer; 
 applying a photoresist mask over the first oxide layer, the photoresist mask having an opening in the mask that is on top of and smaller than the patterned metal layer; 
 etching the first oxide layer from the patterned metal layer such that a thin oxide bump is left at the edge of the patterned metal layer; and 
 depositing a second HDP CVD oxide layer over the first oxide layer, the thin oxide bump, and the patterned metal layer such that the second HDP CVD oxide layer mitigates the size of the thin oxide bump. 
 
     
     
       2. The method of  claim 1  wherein in photoresist mask is sized and positioned to prevent etching of the oxide layer adjacent the patterned metal layer. 
     
     
       3. The method of  claim 2  further comprised of:
 depositing and patterning a second metal layer over the second HDP CVD oxide layer. 
 
     
     
       4. The method of  claim 3  further comprised of:
 depositing a passivation layer over the second metal layer and the second HDP 
 CVD oxide layer. 
 
     
     
       5. The method of  claim 1  wherein the dielectric layer on the substrate is a silicon dioxide layer. 
     
     
       6. The method of  claim 1  wherein the method is used in the fabrication of BAW resonator. 
     
     
       7. The method of  claim 1  wherein the method is used in the fabrication of coupled BAW resonators. 
     
     
       8. In the fabrication of a circuit, a method of maintaining a planar surface on an oxide layer deposited over a patterned layer of metal on a substrate comprising:
 a) depositing the metal layer; 
 b) patterning the metal layer; 
 c) depositing an oxide layer over the patterned metal layer and surrounding substrate using high density plasma chemical vapor deposition to a thickness substantially equal to the thickness of the metal layer; 
 d) masking and etching the oxide layer from the patterned metal layer, the masking being sized and positioned to prevent etching of the oxide layer adjacent the patterned metal layer; and 
 e) depositing a second HDP CVD oxide layer over the patterned metal layer and surrounding oxide layer; 
 f) repeating a) through e) at least once; 
 g) then repeating a) through d); 
 h) chemical mechanical polishing the patterned metal and oxide layers of g), and; 
 i) depositing a piezoelectric layer.