Semiconductor memory device highly integrated in direction of columns

Abstract

First and second read word lines are provided in each set made of two adjacent rows. First, second, third, and fourth read bit lines are provided in each column. Each of the first and second read word lines is connected to memory cells in a corresponding one of the sets. Each of the first and third read bit lines is connected to a memory cell in one row in each of the sets, out of memory cells in a corresponding one of the columns. Each of the second and fourth read bit lines is connected to a memory cell in the other row in each of the sets, out of the memory cells in the corresponding one of the columns.

1. A semiconductor memory device, comprising:
 a memory cell array having a plurality of memory cells arranged in rows and columns; 
 first and second read word lines arranged corresponding to each of sets, each set composed of a pair of adjacent ones of the rows; and 
 first, second, third, and fourth read bit lines provided in each of the columns, wherein 
 each of said first and second read word lines is connected to first and second memory cells in a corresponding one of the sets, the first and second memory cells are arranged adjacently to each other in one column, and 
 each of said first and third read bit lines is connected to the first memory cell in a corresponding one of the columns, and each of said second and fourth read bit lines is connected to the second memory cell in the corresponding one of the columns. 
 
     
     
       2. The semiconductor memory device according to  claim 1 , further comprising
 a first read row decoder controlling activation of said first read word line based on a set-specifying address in a first read address, 
 a second read row decoder controlling activation of said second read word line based on a set-specifying address in a second read address, 
 a first selector which is provided in each of the columns, and to which said first read bit line and said second read bit line are connected, 
 a second selector which is provided in each of the columns, and to which said third read bit line and said fourth read bit line are connected, 
 a first read column decoder providing control as to an output signal of which first selector out of the first selectors in all of the columns should be selected, based on a column-specifying address in said first read address, and 
 a second read column decoder providing control as to an output signal of which second selector out of the second selectors in all of the columns should be selected, based on a column-specifying address in said second read address, wherein 
 said first selector selects and outputs a signal of any of said first read bit line and said second read bit line, based on a row-in-set-specifying address in said first read address, and 
 said second selector selects and outputs a signal of any of said third read bit line and said fourth read bit line, based on a row-in-set-specifying address in said second read address. 
 
     
     
       3. The semiconductor memory device according to  claim 2 , further comprising a precharge circuit precharging said first, second, third, and fourth read bit lines prior to data readout from said memory cells. 
     
     
       4. The semiconductor memory device according to  claim 3 , further comprising
 a write word line provided in each of the rows, and 
 a pair of a write bit line of a positive phase and a write bit line of a negative phase, provided in each of the columns, wherein 
 each of said write word lines is connected to memory cells in a corresponding one of the rows, and 
 each of said pairs of the write bit lines is connected to memory cells in a corresponding one of the columns. 
 
     
     
       5. The semiconductor memory device according to  claim 4 , wherein
 each of said memory cells includes 
 a first CMOS inverter made of a first MOS transistor of a first conductivity type and a second MOS transistor of a second conductivity type, 
 a second CMOS inverter made of a third MOS transistor of the first conductivity type and a fourth MOS transistor of the second conductivity type, 
 said first CMOS inverter having an input terminal which is identified as a first storage terminal connected to an output terminal of said second CMOS inverter, 
 said second CMOS inverter having an input terminal which is identified as a second storage terminal connected to an output terminal of said first CMOS inverter, 
 a fifth MOS transistor of the second conductivity type, connected between said write bit line of the negative phase and said second storage terminal, and having a control electrode to which said write word line is connected, 
 a sixth MOS transistor of the second conductivity type, connected between said write bit line of the positive phase and said first storage terminal, and having a control electrode to which said write word line is connected, 
 a seventh MOS transistor of the second conductivity type and an eighth MOS transistor of the second conductivity type, connected in series between a ground node and one of said first read bit line and said second read bit line, and 
 a ninth MOS transistor of the second conductivity type and a tenth MOS transistor of the second conductivity type, connected in series between the ground node and one of said third read bit line and said fourth read bit line, wherein 
 a control electrode of said seventh MOS transistor is connected to said first read word line, 
 a control electrode of said ninth MOS transistor is connected to said second read word line, and 
 a control electrode of said eighth MOS transistor and a control electrode of said tenth MOS transistor are connected to said second storage terminal. 
 
     
     
       6. The semiconductor memory device according to  claim 5 , wherein
 said semiconductor memory device includes a first-layer metal interconnection connected to any of said first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth MOS transistors via a contact hole, 
 said pair of the write bit lines is placed in a direction of the columns with use of a second-layer metal interconnection serving as an upper layer with respect to said first-layer metal interconnection, and 
 said first, second, third, and fourth read bit lines are placed in the direction of the columns with use of said second-layer metal interconnection. 
 
     
     
       7. The semiconductor memory device according to  claim 6 , wherein
 in each of the columns, said first, second, third, and fourth read bit lines corresponding to said each of the columns are placed in the direction of the columns, and 
 in each of the columns, said pair of the write bit lines corresponding to said each of the columns is placed in the direction of the columns. 
 
     
     
       8. The semiconductor memory device according to  claim 7 , further comprising
 a power supply line and a ground line, placed in the direction of the columns with use of said second-layer metal interconnection, wherein 
 said ground line, or said ground line and said power supply line is/are arranged between any of the write bit lines in said pair and any of said first, second, third, and fourth read bit lines. 
 
     
     
       9. The semiconductor memory device according to  claim 6 , wherein
 said write word line is placed in a direction of the rows with use of a third-layer metal interconnection serving as an upper layer with respect to said second-layer metal interconnection, and 
 said first and second read word lines are placed in the direction of the rows with use of said third-layer metal interconnection. 
 
     
     
       10. The semiconductor memory device according to  claim 9 , wherein in each of the rows, said write word line corresponding to said each of the rows is placed in the direction of the rows, and
 in one row in each of the sets, said first read word line corresponding to said each of the sets is placed in the direction of the rows, and in the other row in each of the sets, said second read word line corresponding to said each of the sets is placed in the direction of the rows. 
 
     
     
       11. A semiconductor memory device, comprising:
 a memory cell array having a plurality of memory cells arranged in rows and columns; 
 a pair of a read word line of a positive phase and a read word line of a negative phase arranged corresponding to each sets, each set composed of a pair of adjacent ones of the rows; and 
 a first read bit line and a second read bit line, provided in each of the columns, wherein 
 each of said pairs of the read word lines is connected to first and second memory cells in a corresponding one of the sets, the first and second memory cells are arranged adjacently to each other in one column, and 
 said first read bit line is connected to the first memory cell in a corresponding one of the columns, and said second read bit line is connected to the second memory cell in the corresponding one of the columns. 
 
     
     
       12. The semiconductor memory device according to  claim 11 , further comprising
 a read row decoder controlling activation of said pair of the read word lines based on a set-specifying address in a read address, 
 a selector which is provided in each of the columns, and to which said first read bit line and said second read bit line are connected, and 
 a read column decoder providing control as to an output signal of which selector out of the selectors in all of the columns should be selected, based on a column-specifying address in the read address, wherein 
 said selector selects and outputs a signal of any of said first read bit line and said second read bit line, based on a row-in-set-specifying address in said read address. 
 
     
     
       13. The semiconductor memory device according to  claim 12 , further comprising
 a write word line provided in each of the rows, and 
 a pair of a write bit line of a positive phase and a write bit line of a negative phase, provided in each of the columns, wherein 
 each of said write word lines is connected to memory cells in a corresponding one of the rows, and 
 each of said pairs of the write bit lines is connected to memory cells in a corresponding one of the columns. 
 
     
     
       14. The semiconductor memory device according to  claim 13 , wherein
 each of said memory cells includes 
 a first CMOS inverter made of a first MOS transistor of a first conductivity type and a second MOS transistor of a second conductivity type, 
 a second CMOS inverter made of a third MOS transistor of the first conductivity type and a fourth MOS transistor of the second conductivity type, 
 said first CMOS inverter having an input terminal which is identified as a first storage terminal connected to an output terminal of said second CMOS inverter, 
 said second CMOS inverter having an input terminal which is identified as a second storage terminal connected to an output terminal of said first CMOS inverter, 
 a fifth MOS transistor of the second conductivity type, connected between said write bit line of the negative phase and said second storage terminal, and having a control electrode to which said write word line is connected, 
 a sixth MOS transistor of the second conductivity type, connected between said write bit line of the positive phase and said first storage terminal, and having a control electrode to which said write word line is connected, 
 a third CMOS inverter made of a seventh MOS transistor of the first conductivity type and an eighth MOS transistor of the second conductivity type, and 
 a transfer gate made of a ninth MOS transistor of the first conductivity type and a tenth MOS transistor of the second conductivity type, wherein 
 an output terminal of said third CMOS inverter is connected to said second storage terminal, and 
 said transfer gate is connected between an input of said third CMOS inverter and one of said first read bit line and said second read bit line, and has one control electrode to which the read word line of the positive phase is connected, and has the other control electrode to which the read word line of the negative phase is connected. 
 
     
     
       15. The semiconductor memory device according to  claim 14 , wherein
 said semiconductor memory device includes a first-layer metal interconnection connected to any of said first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth MOS transistors via a contact hole, 
 said pair of the write bit lines is placed in a direction of the columns with use of a second-layer metal interconnection serving as an upper layer with respect to said first-layer metal interconnection, and 
 said first and second read bit lines are placed in the direction of the columns with use of said second-layer metal interconnection. 
 
     
     
       16. The semiconductor memory device according to  claim 13 , wherein
 each of said memory cells includes 
 a first CMOS inverter made of a first MOS transistor of a first conductivity type and a second MOS transistor of a second conductivity type, 
 a second CMOS inverter made of a third MOS transistor of the first conductivity type and a fourth MOS transistor of the second conductivity type, 
 said first CMOS inverter having an input terminal which is identified as a first storage terminal connected to an output terminal of said second CMOS inverter, 
 said second CMOS inverter having an input terminal which is identified as a second storage terminal connected to an output terminal of said first CMOS inverter, 
 a fifth MOS transistor of the second conductivity type, connected between said write bit line of the negative phase and said second storage terminal, and having a control electrode to which said write word line is connected, 
 a sixth MOS transistor of the second conductivity type, connected between said write bit line of the positive phase and said first storage terminal, and having a control electrode to which said write word line is connected, and 
 a tristate inverter made of a seventh MOS transistor of the first conductivity type, an eighth MOS transistor of the first conductivity type, a ninth MOS transistor of the second conductivity type, and a tenth MOS transistor of the second conductivity type, all connected in series between a power supply node and a ground node, wherein 
 an input of said tristate inverter is connected to one of said first read bit line and said second read bit line, 
 an output of said tristate inverter is connected to said second storage terminal, 
 a control electrode of said eighth MOS transistor is connected to said read word line of the negative phase, and 
 a control electrode of said ninth MOS transistor is connected to said read word line of the positive phase. 
 
     
     
       17. The semiconductor memory device according to  claim 16 , wherein
 said semiconductor memory device includes a first-layer metal interconnection connected to any of said first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, and tenth MOS transistors via a contact hole, 
 said pair of the write bit lines is placed in a direction of the columns with use of a second-layer metal interconnection serving as an upper layer with respect to said first-layer metal interconnection, and 
 said first and second read bit lines are placed in the direction of the columns with use of said second-layer metal interconnection. 
 
     
     
       18. The semiconductor memory device according to  claim 17 , wherein
 in each of the columns, said first and second read bit lines corresponding to said each of the columns are placed in the direction of the columns, and 
 in each of the columns, said pair of the write bit lines corresponding to said each of the columns is placed in the direction of the columns. 
 
     
     
       19. The semiconductor memory device according to  claim 18 , further comprising a power supply line and a ground line, placed in the direction of the columns with use of said second-layer metal interconnection, wherein
 said power supply line and said ground line are arranged between any of the write bit lines in said pair and any of said first and second read bit lines. 
 
     
     
       20. The semiconductor memory device according to  claim 18 , further comprising a power supply line placed in the direction of the columns with use of said second-layer metal interconnection, wherein
 said power supply line is arranged between said first read bit line and said second read bit line. 
 
     
     
       21. The semiconductor memory device according to  claim 17 , wherein
 said write word line is placed in the direction of the rows with use of a third-layer metal interconnection serving as an upper layer with respect to said second-layer metal interconnection, and 
 said pair of the read word lines is placed in the direction of the rows with use of said third-layer metal interconnection. 
 
     
     
       22. The semiconductor memory device according to  claim 21 , wherein
 in each of the rows, said write word line corresponding to said each of the rows is placed in the direction of the rows, and 
 in one row in each of the sets, said read word line of the positive phase corresponding to said each of the sets is placed in the direction of the rows, and in the other row in each of the sets, said read word line of the negative phase corresponding to said each of the sets is placed in the direction of the rows.