Semiconductor device

Abstract

A semiconductor device is provided. A pull-up slew rate controller receives a first driving control signal generated in a first mode of operation, a second driving control signal generated in a second mode of operation, and data, and upon a first transition of the data, sequentially activates the data and a first pull-up delayed signal having different delay times in the first mode of operation and sequentially activates the data and the first to third pull-up delayed signals having different delay times in the second mode of operation. A pull-up driving unit sequentially pulls a data output terminal up in response to the data and the first to third pull-up delayed signals. A pull-down slew rate controller, upon a second transition of the data, sequentially activates the data and the first pull-down delayed signal having different delay times in the first mode of operation and sequentially activates the data and the first to third pull-down delayed signals having different delay times in the second mode of operation. A pull-down driving unit sequentially pulls the data output terminal down in response to the data and the first to third pull-down delayed signals.

1. A semiconductor device comprising:
 a pull-up slew rate controller configured to receive a first driving control signal generated in a first mode of operation, a second driving control signal generated in a second mode of operation, and data, and upon a first transition of the data, to sequentially activate the data and a first pull-up delayed signal having different delay times in the first mode of operation and to sequentially activate the data and the first pull-up delayed signal, a second pull-up delayed signal and a third pull-up delayed signal, each having different delay times in the second mode of operation; 
 a pull-up driving unit configured to sequentially pull a data output terminal up in response to the data and the first pull-up delayed signal, the second pull-up delayed signal and the third pull-up delayed signal; 
 a pull-down slew rate controller configured to, upon a second transition of the data, sequentially activate the data and a first pull-down delayed signal having different delay times in the first mode of operation and to sequentially activate the data and the first pull-down delayed signal, a second pull-down delayed signal and a third pull-down delayed signal, each having different delay times in the second mode of operation; and 
 a pull-down driving unit configured to sequentially pull the data output terminal down in response to the data and the first pull-down delayed signal, the second pull-down delayed signal and the third pull-down delayed signal. 
 
     
     
       2. The device of  claim 1 , wherein the pull-up slew rate controller comprises:
 a first asymmetrical delay unit configured to delay the data by a greater delay time upon the first transition of the data than upon the second transition to output the first pull-up delayed signal; 
 a second asymmetrical delay unit configured to delay the first pull-up delayed signal by a greater delay time upon a first transition of the first pull-up delayed signal than upon a second transition thereof to output the second pull-up delayed signal; and 
 a third asymmetrical delay unit configured to delay the second pull-up delayed signal by a greater delay time upon a first transition of the second pull-up delayed signal than upon a second transition thereof to output the third pull-up delayed signal. 
 
     
     
       3. The device of  claim 2 , wherein each of the first asymmetrical delay unit, the second asymmetrical delay unit and the third asymmetrical delay unit comprises:
 a NAND gate configured to receive one of the data and the first pull-up delayed signal and second pull-up delayed signal, to receive the first driving control signal or the second driving control signal, and perform a NAND operation on the one of the data and the first pull-up delayed signal and the second pull-up delayed signal and the first driving control signal or the second driving control signal; and 
 a plurality of inverters each including pull-up and pull-down devices having different channel sizes and configured to sequentially invert and delay an output signal of the NAND gate, wherein each inverter delays the output signal of the NAND gate through one having a smaller channel size of the pull-up and pull-down devices upon the first transition of the data than upon the second transition. 
 
     
     
       4. The device of  claim 2 , wherein each of the first asymmetrical delay unit, the second asymmetrical delay unit and the third asymmetrical delay unit comprises:
 a NAND gate configured to receive one of the data and the first pull-up delayed signal and the second pull-up delayed signal, receive the first driving control signal or the second driving control signal, and perform a NAND operation on the one of the data and the first pull-up delayed signal and the second pull-up delayed signal and the first driving control signal or the second driving control signal; 
 an inverter group including an even number of inverters and configured to delay an output signal of the NAND gate by a predetermined time; and 
 a NOR gate configured to perform a NOR operation on the output signal of the NAND gate and an output signal of the inverter group to output the first pull-up delayed signal, the second pull-up delayed signal and the third pull-up delayed signal. 
 
     
     
       5. The device of  claim 1 , wherein the pull-down slew rate controller comprises:
 a first asymmetrical delay unit configured to delay the data by a greater delay time upon the second transition of the data than upon the first transition to output the first pull-down delayed signal; 
 a second asymmetrical delay unit configured to delay the first pull-down delayed signal by a greater delay time upon a second transition of the first pull-down delayed signal than upon a first transition thereof to output the second pull-down delayed signal; and 
 a third asymmetrical delay unit configured to delay the second pull-down delayed signal by a greater delay time upon a second transition of the second pull-down delayed signal than upon a first transition thereof to output the third delay pull-down data. 
 
     
     
       6. The device of  claim 5 , wherein each of the first asymmetrical delay unit, the second asymmetrical delay unit and the third asymmetrical delay unit comprises:
 a NOR gate configured to receive one of the data and the first pull-down delayed signal and the second pull-down delayed signal, to receive a first driving control signal or second inverted driving control signal, and perform a NOR operation on the one of the data and the first pull-down delayed signal and the second pull-down delayed signal and the first inverted driving control signal or second inverted driving control signal; and 
 a plurality of inverters each including pull-up and pull-down devices having different line widths and configured to sequentially invert and delay an output signal of the NOR gate, wherein each inverter delays the output signal of the NOR gate through one having a smaller line width of the pull-up and pull-down devices upon the first transition of the data than upon the second transition. 
 
     
     
       7. The device of  claim 5 , wherein each of the first asymmetrical delay unit, the second asymmetrical delay unit and the third asymmetrical delay unit comprises:
 a NOR gate configured to receive one of the data and the first pull-up delayed signal and the second pull-up delayed signal, to receive the first driving control signal or the second driving control signal, and to perform a NOR operation on the one of the data and the first pull-up delayed signal and the second pull-up delayed signal and the first driving control signal or the second driving control signal; 
 an inverter group comprising an even number of inverters and configured to delay an output signal of the NOR gate by a predetermined time; and 
 a NAND gate configured to receive the output signal of the NOR gate and an output signal of the inverter group and configured to perform a NAND operation on the output signal of the NOR gate and the output signal of the inverter group to output the first pull-down delayed signal, the second pull-down delayed signal, and the third pull-down delayed signal. 
 
     
     
       8. The device of  claim 1 , wherein the pull-up driving unit comprises:
 a pull-up pre-driver configured to invert the data and the first pull-up delayed signal, the second pull-up delayed signal and the third pull-up delayed signal to output a plurality of pull-up control signals; and 
 a pull-up driver including a first pull-up device, a second pull-up device, a third pull-up device and a fourth pull-up device for pulling the data output terminal up in response to the respective pull-up control signals, and 
 wherein the first pull-up device and the second pull-up device are sequentially turned on in response to the first pull-up control signal and the second pull-up control signal in the first mode of operation, and the first pull-up device, the second pull-up device, the third pull-up device and the fourth pull-up device are sequentially turned on in response to the first pull-up control signal, the second pull-up control signal, the third pull-up control signal, and the fourth pull-up control signal in the second mode of operation. 
 
     
     
       9. The device of  claim 1 , wherein the pull-down driving unit comprises:
 a pull-down pre-driver configured to invert the data and the first pull-down delayed signal, the second pull-down delayed signal and the third pull-down delayed signal to output a plurality of pull-down control signals; and 
 a pull-down driver including a first pull-down device, a second pull-down device and a fourth pull-down device for pulling the data output terminal down in response to the respective pull-down control signals, and 
 wherein the first pull-down device and the second pull-down device are sequentially turned on in response to the first pull-down control signal and the second pull-down control signal in the first mode of operation, and the first pull-down device, the second pull-down device, the third pull-down device to fourth pull-down device are sequentially turned on in response to the first pull-down control signal, the second pull-down control signal, the third pull-down control signal and the fourth pull-down control signal in the second mode of operation. 
 
     
     
       10. A pull-up pull-down driving apparatus comprising:
 a pull-up driver comprising a first pull-up transistor, a second pull-up transistor, a third pull-up transistor and a fourth pull-up transistor coupled in parallel to a data output terminal for pulling the data output terminal up in response to respective pull-up control signals, the first pull-up transistor and the second pull-up transistor being sequentially turned on in response to a first pull-up control signal and a second pull-up control signal in a half driving operation, and the first pull-up transistor, the second pull-up transistor, the third pull-up transistor and the fourth pull-up transistor being sequentially turned on in response to the first pull-up control signal, the second pull-up control signal a third pull-up control signal and a fourth pull-ups control signal in a full driving operation, 
 a pull-down driver comprising a first pull-down transistor, a second pull-down transistor, a third pull-down transistor and a fourth pull-down transistor for pulling the data output terminal down in response to respective pull-down control signals, the first pull-down transistor and the second pull-down transistor being sequentially turned on in response to a first pull-down control signal and a second pull-down control signal in the half driving operation, and the first pull-down transistor, the second pull-down transistor, the third pull-down transistor and fourth pull-down transistor being sequentially turned on in response to the first pull-down control signal, the second pull-down control signal, a third pull-down control signal and a fourth pull-down control signal in the full driving operation, and 
 a pull-up pre-driver coupled to the pull-up driver and configured to invert data being provided to the data output terminal and a first pull-up delayed signal, a second pull-up delayed signal and a third pull-up delayed signal to output the respective first pull-up control signal, the second pull-up control signal, the third pull up control signal and the fourth pull-up control signal. 
 
     
     
       11. A pull-up pull-down driving apparatus comprising:
 a pull-up driver comprising a first pull-up transistor, a second pull-up transistor, a third pull-up transistor and a fourth pull-up transistor coupled in parallel to a data output terminal for pulling the data output terminal up in response to respective pull-up control signals, the first pull-up transistor and the second pull-up transistor being sequentially turned on in response to a first pull-up control signal and a second pull-up control signal in a half driving operation, and the first pull-up transistor, the second pull-up transistor, the third pull-up transistor and the fourth pull-up transistor being sequentially turned on in response to the first pull-up control signal, the second pull-up control signal, a third pull-up control signal, and a fourth pull-up control signal in a full driving operation, 
 a pull-down driver comprising a first pull-down transistor, a second pull-down transistor, a third pull-down transistor and a fourth pull-down transistor for pulling the data output terminal down in response to respective pull-down control signals, the first pull-down transistor and the second pull-down transistor being sequentially turned on in response to a first pull-down control signal and a second pull-down control signal in the half driving operation, and the first pull-down transistor, the second pull-down transistor, the third pull-down transistor and fourth pull-down transistor being sequentially turned on in response to the first pull-down control signal, the second pull-down control signal, a third pull-down control signal and a fourth pull-down control signal in the full driving operation, and 
 a pull-down pre-driver coupled to the pull-down driver and configured to invert a data being provided to the data output terminal and a first pull-down delayed signal, a second pull-down delayed signal and a third pull-down delayed signal to output the respective first pull-down control signal, the second pull-down control signal, the third pull-down control signal and the fourth pull-down control signal.