P
US8026147B2ActiveUtilityPatentIndex 45

Method of fabricating a semiconductor microstructure

Assignee: SAMSUNG ELECTRONICS CO LTDPriority: Aug 13, 2009Filed: Aug 13, 2010Granted: Sep 27, 2011
Est. expiryAug 13, 2029(~3.1 yrs left)· nominal 20-yr term from priority
Inventors:CHOI YONGSOONBYUN KYUNG-MOONHONG EUNKEEBAEK EUN-KYUNG
H10P 50/283H10D 1/716H10D 1/042H10P 50/00H10B 12/033H10B 12/318
45
PatentIndex Score
1
Cited by
8
References
11
Claims

Abstract

Provided is a method of fabricating a semiconductor microstructure, the method including forming a lower material layer on a semiconductor substrate, the lower material layer including a nitride of a Group III-element; forming a mold material layer on the lower material layer; forming an etching mask on the mold material layer, the etching mask being for forming a structure in the mold material layer; anisotropic-etching the mold material layer and the lower material layer by using the etching mask; and isotropic-etching the mold material layer and the lower material layer.

Claims

exact text as granted — not AI-modified
1. A method of fabricating a semiconductor microstructure, the method comprising:
 forming a lower material layer on a semiconductor substrate, the lower material layer comprising a nitride of a Group III-element; 
 forming a mold material layer on the lower material layer; 
 forming an etching mask on the mold material layer, the etching mask being for forming a structure in the mold material layer; 
 anisotropic-etching the mold material layer and the lower material layer by using the etching mask; and 
 isotropic-etching the mold material layer and the lower material layer. 
 
     
     
       2. The method of  claim 1 , wherein the lower material layer comprises boron nitride, aluminum nitride, or a mixture thereof. 
     
     
       3. The method of  claim 1 , further comprising forming a supporting material layer on the mold material layer, prior to the forming of the etching mask. 
     
     
       4. The method of  claim 3 , wherein the supporting material layer comprises a silicon nitride. 
     
     
       5. The method of  claim 3 , wherein the supporting material layer consists of a silicon nitride. 
     
     
       6. The method of  claim 1 , wherein the mold material layer comprises a silicon oxide. 
     
     
       7. The method of  claim 1 , wherein, in the isotropic-etching of the mold material layer and the lower material layer, an etchant comprising at least one of the group consisting of sulphuric acid (H 2 SO 4 ), deionized water, and SC-1 solution is used for isotropic-etching the mold material layer and the lower material layer. 
     
     
       8. The method of  claim 1 , wherein the structure is a via hole. 
     
     
       9. The method of  claim 8 , further comprising:
 forming a bottom electrode on the inner surface of the via hole; and 
 sequentially forming a dielectric layer and a top electrode on the bottom electrode. 
 
     
     
       10. The method of  claim 1 , further comprising forming a supporting material layer on the mold material layer, prior to the forming of the etching mask,
 in the isotropic-etching of the mold material layer and the lower material layer, an etchant comprising at least one of the group consisting of sulphuric acid (H 2 SO 4 ), deionized water, and SC-1 solution is used for isotropic-etching the mold material layer and the lower material layer, and 
 the lower material layer is etched faster than the supporting material layer by the etchant. 
 
     
     
       11. The method of  claim 1 , wherein the lower material layer is formed by using a chemical vapor deposition (CVD) method.

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