Tunneling field effect transistor switch device

Abstract

A tunneling field effect transistor (TFET) device includes a semiconductor substrate having a layer of relatively intermediate bandgap semiconductor material, a layer of relatively low bandgap semiconductor material overlying the layer of relatively intermediate bandgap semiconductor material, and a layer of relatively high bandgap semiconductor material overlying the layer of relatively low bandgap semiconductor material. The TFET device includes a source region, a drain region, and a channel region defined in the semiconductor substrate. The TFET device also has a gate structure overlying at least a portion of the channel region. The source region is highly doped with an impurity dopant having a first conductivity type, and the drain region is highly doped with an impurity dopant having a second conductivity type. The layer of relatively low bandgap semiconductor material promotes tunneling at a first junction between the source region and the channel region, and the layer of relatively high bandgap semiconductor material inhibits tunneling at a second junction between the source region and the channel region.

1. A semiconductor device comprising:
 a first layer of semiconductor material; 
 a second layer of semiconductor material overlying the first layer of semiconductor material, the second layer of semiconductor material comprising a relatively low bandgap material; 
 a third layer of semiconductor material overlying the second layer of semiconductor material, the third layer of semiconductor material comprising a relatively high bandgap material; 
 a gate structure formed on the third layer of semiconductor material; 
 a source region defined in the third layer of semiconductor material and in the second layer of semiconductor material; and 
 a drain region defined in the third layer of semiconductor material and in the second layer of semiconductor material. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein:
 the semiconductor device is an N-type tunneling field effect transistor (NTFET); 
 the first layer of semiconductor material is lightly doped with an N-type impurity; 
 the source region is heavily doped with a P-type impurity; and 
 the drain region is heavily doped with an N-type impurity. 
 
     
     
       3. The semiconductor device of  claim 1 , wherein:
 the semiconductor device is a P-type tunneling field effect transistor (PTFET); 
 the first layer of semiconductor material is lightly doped with a P-type impurity; 
 the source region is heavily doped with an N-type impurity; and 
 the drain region is heavily doped with a P-type impurity. 
 
     
     
       4. The semiconductor device of  claim 1 , wherein:
 the first layer of semiconductor material comprises silicon; 
 the second layer of semiconductor material comprises silicon germanium; and 
 the third layer of semiconductor material comprises silicon carbon. 
 
     
     
       5. The semiconductor device of  claim 4 , wherein:
 the second layer of semiconductor material comprises epitaxially grown silicon germanium; and 
 the third layer of semiconductor material comprises epitaxially grown silicon carbon. 
 
     
     
       6. The semiconductor device of  claim 1 , wherein the first layer of semiconductor material comprises a relatively intermediate bandgap material. 
     
     
       7. The semiconductor device of  claim 1 , wherein the source region is defined in the third layer of semiconductor material, in the second layer of semiconductor material, and in the first layer of semiconductor material. 
     
     
       8. The semiconductor device of  claim 1 , wherein the drain region is defined in the third layer of semiconductor material, in the second layer of semiconductor material, and in the first layer of semiconductor material. 
     
     
       9. The semiconductor device of  claim 1 , wherein:
 the relatively low bandgap material of the second layer of semiconductor material promotes tunneling at a first source junction defined in the second layer of semiconductor material; and 
 the relatively high bandgap material of the third layer of semiconductor material inhibits tunneling at a second source junction defined in the third layer of semiconductor material. 
 
     
     
       10. A semiconductor switch device comprising:
 a semiconductor substrate; 
 a gate structure formed on the semiconductor substrate; 
 a source region defined in the semiconductor substrate, the source region being heavily doped with a first conductivity type impurity; 
 a drain region defined in the semiconductor substrate, the drain region being heavily doped with a second conductivity type impurity; and 
 a channel region defined in the semiconductor substrate between the source region and the drain region, at least a portion of the channel region underlying the gate structure; wherein 
 in the channel region, the semiconductor substrate comprises an upper layer formed from a relatively high bandgap material, a lower layer formed from a relatively low bandgap material, and a lowermost layer formed from a relatively intermediate bandgap material. 
 
     
     
       11. The semiconductor switch device of  claim 10 , wherein:
 the lower layer comprises silicon germanium; and 
 the upper layer comprises silicon carbon. 
 
     
     
       12. The semiconductor switch device of  claim 10 , wherein:
 in the source region, the semiconductor substrate comprises the upper layer and the lower layer; and 
 in the drain region, the semiconductor substrate comprises the upper layer and the lower layer. 
 
     
     
       13. The semiconductor switch device of  claim 10 , wherein:
 the relatively low bandgap material of the lower layer promotes tunneling at a first junction between the source region and the channel region, the first junction located in the lower layer; and 
 the relatively high bandgap material of the upper layer inhibits tunneling at a second junction between the source region and the channel region, the second junction located in the upper layer. 
 
     
     
       14. A tunneling field effect transistor (TFET) device comprising:
 a semiconductor substrate comprising a layer of relatively intermediate bandgap semiconductor material, a layer of relatively low bandgap semiconductor material overlying the layer of relatively intermediate bandgap semiconductor material, and a layer of relatively high bandgap semiconductor material overlying the layer of relatively low bandgap semiconductor material; 
 a source region defined in the semiconductor substrate, the source region being highly doped with impurity dopant having a first conductivity type; 
 a drain region defined in the semiconductor substrate, the drain region being highly doped with impurity dopant having a second conductivity type; 
 a channel region defined in the semiconductor substrate between the source region and the drain region; and 
 a gate structure formed on the semiconductor substrate, the gate structure overlying at least a portion of the channel region; 
 wherein the layer of relatively low bandgap semiconductor material promotes tunneling at a first junction between the source region and the channel region; and 
 the layer of relatively high bandgap semiconductor material inhibits tunneling at a second junction between the source region and the channel region. 
 
     
     
       15. The TFET device of  claim 14 , wherein the layer of relatively intermediate bandgap semiconductor material is lightly doped with impurity dopant having the second conductivity type. 
     
     
       16. The TFET device of  claim 14 , wherein:
 the layer of relatively intermediate bandgap semiconductor material comprises silicon; 
 the layer of relatively low bandgap semiconductor material comprises silicon germanium; and 
 the layer of relatively high bandgap semiconductor material comprises silicon carbon. 
 
     
     
       17. The TFET device of  claim 14 , wherein:
 a first portion of the source region is defined in the layer of relatively high bandgap semiconductor material; and 
 a second portion of the source region is defined in the layer of relatively low bandgap semiconductor material. 
 
     
     
       18. The TFET device of  claim 17 , wherein a third portion of the source region is defined in the layer of relatively intermediate bandgap semiconductor material. 
     
     
       19. The TFET device of  claim 17 , wherein:
 a first portion of the drain region is defined in the layer of relatively high bandgap semiconductor material; and 
 a second portion of the drain region is defined in the layer of relatively low bandgap semiconductor material. 
 
     
     
       20. The TFET device of  claim 19 , wherein a third portion of the drain region is defined in the layer of relatively intermediate bandgap semiconductor material.