Method for fabrication of a semiconductor device and structure

Abstract

A method of manufacturing a semiconductor wafer, the method including: providing a base wafer including a semiconductor substrate, metal layers and first alignment marks; transferring a monocrystalline layer on top of the metal layers, wherein the monocrystalline layer includes second alignment marks; and performing a lithography using at least one of the first alignment marks in a first direction and at least one of the second alignment marks in a second direction.

1. A method of manufacturing a semiconductor wafer, the method comprising:
 providing a base wafer comprising a semiconductor substrate, metal layers and first alignment marks; 
 transferring a monocrystalline layer on top of said metal layers, wherein said monocrystalline layer comprises second alignment marks; and 
 performing a lithography using at least one of said first alignment marks in a first direction and at least one of said second alignment marks in a second direction. 
 
     
     
       2. The method according to  claim 1  wherein:
 said monocrystalline layer further comprises transistors formed therein. 
 
     
     
       3. The method according to  claim 1  wherein said transferring comprises:
 performing layer transfer of said monocrystalline layer to a carrier; and 
 performing layer transfer of said monocrystalline layer on top of said metal layers from said carrier. 
 
     
     
       4. The method according to  claim 1 , further comprising:
 etching said monocrystalline layer to form a plurality of transistors. 
 
     
     
       5. The method according to  claim 1 , further comprising:
 performing gate replacement in said monocrystalline layer. 
 
     
     
       6. The method according to  claim 1 , further comprising:
 optical annealing of at least one region of said monocrystalline layer. 
 
     
     
       7. The method according to  claim 1 , wherein:
 said monocrystalline layer comprises a repeating pattern. 
 
     
     
       8. A method of manufacturing a semiconductor wafer, the method comprising:
 providing a base wafer comprising a semiconductor substrate, metal layers, and first alignment marks; 
 preparing a monocrystalline layer comprising semiconductor regions comprising transistors, and second alignment marks; 
 performing layer transfer of said monocrystalline layer on top of said metal layers; and 
 performing gate replacement to at least one of said transistors. 
 
     
     
       9. The method according to  claim 8  further comprising:
 performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks. 
 
     
     
       10. The method according to  claim 8 , wherein said transfer comprises:
 performing layer transfer of said monocrystalline layer to a carrier; and 
 performing layer transfer of said monocrystalline layer on top of said metal layers from said carrier. 
 
     
     
       11. The method according to  claim 8 , further comprising:
 performing a lithography using at least one of said first alignment marks in one direction and at least one of said second alignment marks in another direction. 
 
     
     
       12. The method according to  claim 8 , further comprising:
 optical annealing of at least one region of said monocrystalline layer. 
 
     
     
       13. The method according to  claim 8 , wherein said transistors are of p-type or n-type transistors. 
     
     
       14. A method of manufacturing a semiconductor wafer, the method comprising:
 providing a base wafer comprising a semiconductor substrate, metal layers, and first alignment marks; 
 preparing a monocrystalline layer comprising semiconductor regions, and second alignment marks; 
 performing layer transfer of said monocrystalline layer, first to a carrier and then on top of said metal layers; and 
 performing gate replacement in said monocrystalline layer. 
 
     
     
       15. The method according to  claim 14 , further comprising:
 performing a lithography using an alignment based on a misalignment between said first alignment marks and said second alignment marks. 
 
     
     
       16. The method according to  claim 14 , further comprising:
 performing a lithography using at least one of said first alignment marks in one direction and at least one of said second alignment marks in another direction. 
 
     
     
       17. The method according to  claim 14 , wherein said monocrystalline layer comprises a repeating pattern. 
     
     
       18. The method according to  claim 14 , wherein said transistors are planar transistors. 
     
     
       19. The method according to  claim 14 , wherein said transistors comprise p-type transistors and n-type transistors. 
     
     
       20. The method according to  claim 14 , further comprising:
 optical annealing of at least one region of said monocrystalline layer.