US8080453B1ExpiredUtility

Gate stack having nitride layer

29
Assignee: BLOSSE ALAINPriority: Jun 28, 2002Filed: Jun 28, 2002Granted: Dec 20, 2011
Est. expiryJun 28, 2022(expired)· nominal 20-yr term from priority
H10D 64/01318H10D 30/60H10D 84/0186H10D 84/0149H10D 84/014H10D 84/0177H10D 84/038
29
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Cited by
131
References
11
Claims

Abstract

A semiconductor structure includes a semiconductor substrate, a gate layer containing silicon on the semiconductor substrate, a metallic layer on the gate layer, and a nitride layer on the metallic layer. The gate layer contains a P + region and an N + region.

Claims

exact text as granted — not AI-modified
1. A method of making a semiconductor structure, comprising:
 depositing a first barrier layer on a continuous metallic layer, the continuous metallic layer disposed on a second barrier layer, the second barrier layer disposed on a gate layer comprising silicon, and the gate layer disposed on a semiconductor substrate, wherein the gate layer comprises a P +  region and an N +  region, and wherein the P +  and N +  regions are separated by a region which is on an isolation region of the substrate having a width of at most 0.4 microns; and 
 depositing a nitride layer on the first barrier layer, the depositing comprising a PECVD process carried out at a temperature of approximately 350° C. 
 
     
     
       2. The method of  claim 1 , wherein the continuous metallic layer comprises tungsten. 
     
     
       3. A method of making a semiconductor device, comprising:
 forming a semiconductor structure by the method of  claim 1 , and 
 forming a semiconductor device from the semiconductor structure. 
 
     
     
       4. A method of making an electronic device, comprising:
 forming a semiconductor device by the method of  claim 3 , and 
 forming an electronic device comprising the semiconductor device. 
 
     
     
       5. The method of  claim 1 , further comprising forming a dielectric layer on the nitride layer. 
     
     
       6. The method of  claim 5 , further comprising forming a contact through the dielectric layer to the substrate. 
     
     
       7. The method of  claim 6 , wherein a distance between the gate layer and the contact to the substrate is at most one-half a minimum gate width. 
     
     
       8. The method of  claim 1 , wherein the second barrier layer comprises titanium silicide. 
     
     
       9. The method of  claim 1 , wherein the first barrier layer comprises titanium. 
     
     
       10. The method of  claim 1 , wherein the second barrier layer comprises titanium. 
     
     
       11. The method of  claim 1 , wherein the nitride layer has a thickness of at least 1100 angstroms.

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